Publication detail

Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

SMÉKAL, D. FROLKA, J. HAJNÝ, J.

Original Title

Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

Czech Title

Akcelerace šifrovacího algoritmu AES pomocí programovatelných hradlových polí

English Title

Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

Type

journal article

Language

en

Original Abstract

This article deals with encryption on Field Programmable Gate Array (FPGA). The first part describes current state of symmetric and asymmetric cryptography. The following part focuses on the AES algorithm and its implementation in VHDL language. The last part shows testing results of mentioned implementation on card NFB-40G2 containing FPGA from Xilinx series Virtex-7.

Czech abstract

Článek se zabývá šifrováním na FPGA. První část popisuje současný stav symetrické a asymetrické kryptografie. Následující část se zaměřuje na AES algoritmu a jeho implementace v jazyce VHDL. Poslední část pojednává o testování na kartě NFB - 40G2 s čipem FPGA Virtex-7 Xilinx.

English abstract

This article deals with encryption on Field Programmable Gate Array (FPGA). The first part describes current state of symmetric and asymmetric cryptography. The following part focuses on the AES algorithm and its implementation in VHDL language. The last part shows testing results of mentioned implementation on card NFB-40G2 containing FPGA from Xilinx series Virtex-7.

Keywords

AES, FPGA, VHDL, implementation, encryption, decryption, AddRoundKey, SubBytes, ShiftRows, MixColumns, NetCOPE

Released

05.10.2016

Publisher

IFAC-PapersOnLine

Pages from

384

Pages to

389

Pages count

6

URL

BibTex


@article{BUT127756,
  author="David {Smékal} and Jakub {Frolka} and Jan {Hajný}",
  title="Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays",
  annote="This article deals with encryption on Field Programmable Gate Array (FPGA). The first part describes current state of symmetric and asymmetric cryptography. The following part focuses on the AES algorithm and its implementation in VHDL language. The last part shows testing results of mentioned implementation on card NFB-40G2 containing FPGA from Xilinx series Virtex-7.",
  address="IFAC-PapersOnLine",
  booktitle="14th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2016",
  chapter="127756",
  doi="10.1016/j.ifacol.2016.12.075",
  howpublished="online",
  institution="IFAC-PapersOnLine",
  number="25",
  volume="49",
  year="2016",
  month="october",
  pages="384--389",
  publisher="IFAC-PapersOnLine",
  type="journal article"
}