Publication detail

Voltage-Mode All-Pass Filter Design Using Simple CMOS Transconductor: Non-Ideal Case Study

HERENCSÁR, N. MINAEI, S. KOTON, J. VRBA, K.

Original Title

Voltage-Mode All-Pass Filter Design Using Simple CMOS Transconductor: Non-Ideal Case Study

Czech Title

Voltage-Mode All-Pass Filter Design Using Simple CMOS Transconductor: Non-Ideal Case Study

English Title

Voltage-Mode All-Pass Filter Design Using Simple CMOS Transconductor: Non-Ideal Case Study

Type

conference paper

Language

en

Original Abstract

In this paper, basic transconductor composed of only p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and its utilization for low-voltage first-order voltage-mode (VM) all-pass filter (APF) design is studied. For initial filter design a general structure employing single transconductor and two admittances was proposed. By choosing passive components and considering real behavior of MOSFETs, i.e. parasitic capacitances and output resistances, six specific cases for VM APF design are discussed. SPICE simulations using IBM 0.13 mm level-7 SIGE013 CMOS process BSIM3v3.1 parameters and with +-0.75 V supply voltages are included to support the theoretical results. The selected solution was designed at pole frequency of 219 MHz and consumes 480 uW power.

Czech abstract

In this paper, basic transconductor composed of only p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and its utilization for low-voltage first-order voltage-mode (VM) all-pass filter (APF) design is studied. For initial filter design a general structure employing single transconductor and two admittances was proposed. By choosing passive components and considering real behavior of MOSFETs, i.e. parasitic capacitances and output resistances, six specific cases for VM APF design are discussed. SPICE simulations using IBM 0.13 mm level-7 SIGE013 CMOS process BSIM3v3.1 parameters and with +-0.75 V supply voltages are included to support the theoretical results. The selected solution was designed at pole frequency of 219 MHz and consumes 480 uW power.

English abstract

In this paper, basic transconductor composed of only p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and its utilization for low-voltage first-order voltage-mode (VM) all-pass filter (APF) design is studied. For initial filter design a general structure employing single transconductor and two admittances was proposed. By choosing passive components and considering real behavior of MOSFETs, i.e. parasitic capacitances and output resistances, six specific cases for VM APF design are discussed. SPICE simulations using IBM 0.13 mm level-7 SIGE013 CMOS process BSIM3v3.1 parameters and with +-0.75 V supply voltages are included to support the theoretical results. The selected solution was designed at pole frequency of 219 MHz and consumes 480 uW power.

Keywords

Analog signal processing, all-pass filter, parasitic capacitances, transconductor, voltage-mode circuit

RIV year

2014

Released

01.07.2014

Location

Berlin, Germany

ISBN

978-1-4799-8497-8

Book

Proceedings of the 2015 38th International Conference on Telecommunications and Signal Processing (TSP)

Pages from

677

Pages to

681

Pages count

5

BibTex


@inproceedings{BUT108740,
  author="Norbert {Herencsár} and Shahram {Minaei} and Jaroslav {Koton} and Kamil {Vrba}",
  title="Voltage-Mode All-Pass Filter Design Using Simple CMOS Transconductor: Non-Ideal Case Study",
  annote="In this paper, basic transconductor composed of only p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and its utilization for low-voltage first-order voltage-mode (VM) all-pass filter (APF) design is studied. For initial filter design a general structure employing single transconductor and two admittances was proposed. By choosing passive components and considering real behavior of MOSFETs, i.e. parasitic capacitances and output resistances, six specific cases for VM APF design are discussed. SPICE simulations using IBM 0.13 mm level-7 SIGE013 CMOS process BSIM3v3.1 parameters and with +-0.75 V supply voltages are included to support the theoretical results. The selected solution was designed at pole frequency of 219 MHz and consumes 480 uW power.",
  booktitle="Proceedings of the 2015 38th International Conference on Telecommunications and Signal Processing (TSP)",
  chapter="108740",
  doi="10.1109/TSP.2015.7296349",
  howpublished="print",
  year="2014",
  month="july",
  pages="677--681",
  type="conference paper"
}