Publication detail

Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier

DEMARTINOS, A. PSYCHALINOS, C. KHATEB, F.

Original Title

Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier

Type

journal article in Scopus

Language

English

Original Abstract

A novel configuration of a four-quadrant current multiplier is introduced in this paper. The realization is achieved through the utilization of the voltage translinear principle; the derived topology simultaneously offers the attractive benefits of ultra-low voltage operation and reduced dc power dissipation, in comparison with the corresponding already published multipliers. The above have been achieved without increasing the circuit complexity. The behavior of the multiplier has been evaluated through simulation results, using the Analog Design Environment and the design kit provided by the TSMC 180nm CMOS process.

Keywords

Analog circuits; CMOS analog integrated circuits; Ultra low-voltage analog circuits; Multipliers.

Authors

DEMARTINOS, A.; PSYCHALINOS, C.; KHATEB, F.

RIV year

2014

Released

11. 2. 2014

Publisher

Taylor & Francis

Location

England

ISBN

2168-1724

Periodical

International Journal of Electronics Letters

Year of study

2014 (2)

Number

4

State

United Kingdom of Great Britain and Northern Ireland

Pages from

224

Pages to

233

Pages count

10

URL

http://dx.doi.org/10.1080/21681724.2014.900824

BibTex

@article{BUT105548,
  author="Andreas-Christos {Demartinos} and Costas {Psychalinos} and Fabian {Khateb}",
  title="Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier",
  journal="International Journal of Electronics Letters",
  year="2014",
  volume="2014 (2)",
  number="4",
  pages="224--233",
  doi="10.1080/21681724.2014.900824",
  issn="2168-1724",
  url="http://dx.doi.org/10.1080/21681724.2014.900824"
}