Publication detail

Evaluating Cost/Quality Trade-off Solutions Proposed During a DFT Process

STRNADEL, J.

Original Title

Evaluating Cost/Quality Trade-off Solutions Proposed During a DFT Process

English Title

Evaluating Cost/Quality Trade-off Solutions Proposed During a DFT Process

Type

conference paper

Language

en

Original Abstract

The paper deals with a description of a function for evaluating cost/quality trade-off solutions proposed during an automated DFT process or a designer work. As an input both an original structure of a digital circuit at RT level and a modified one are taken, whereby the circuit with a modified structure is taken as a proposed solution. By comparing with the original circuit structure area and pin overheads and test parameters of the solution are gained and the cost/quality trade-off solution is evaluated.

English abstract

The paper deals with a description of a function for evaluating cost/quality trade-off solutions proposed during an automated DFT process or a designer work. As an input both an original structure of a digital circuit at RT level and a modified one are taken, whereby the circuit with a modified structure is taken as a proposed solution. By comparing with the original circuit structure area and pin overheads and test parameters of the solution are gained and the cost/quality trade-off solution is evaluated.

Keywords

Cost/quality trade-off, digital circuit attributes, user (customer) required attribute value bound(s)

Released

29.04.2002

Publisher

Brno University of Technology

Location

Brno

ISBN

80-214-2116-9

Book

Proceeding of 8th Conference Student EEICT 2002

Pages from

506

Pages to

510

Pages count

5

Documents

BibTex


@inproceedings{BUT10011,
  author="Josef {Strnadel}",
  title="Evaluating Cost/Quality Trade-off Solutions Proposed During a DFT Process",
  annote="The paper deals with a description of a function for evaluating cost/quality trade-off solutions proposed during an automated DFT process or a designer work. As an input both an original structure of a digital circuit at RT level and a modified one are taken, whereby the circuit with a modified structure is taken as a proposed solution. By comparing with the original circuit structure area and pin overheads and test parameters of the solution are gained and the cost/quality trade-off solution is evaluated.",
  address="Brno University of Technology",
  booktitle="Proceeding of 8th Conference Student EEICT 2002",
  chapter="10011",
  institution="Brno University of Technology",
  year="2002",
  month="april",
  pages="506--510",
  publisher="Brno University of Technology",
  type="conference paper"
}