Publication detail

A Design Space Exploration Scheme for High-Level Synthesis Systems

SLLAME M., A., DRÁBEK, V.

Original Title

A Design Space Exploration Scheme for High-Level Synthesis Systems

English Title

A Design Space Exploration Scheme for High-Level Synthesis Systems

Type

conference paper

Language

en

Original Abstract

This paper describes a design exploration methodology that includes scheduling, module selection and clock cycle determination. The underlying methodology is constructed from one preliminary step and three main phases that allow improving every phase independently from the others without affecting their results, as well as it allows incorporation of the proposed techniques in any high-level synthesis system. The method starts by resource-constrained scheduling algorithm, which incorporates a local exploration mechanism to explore the design points so that each change in the resource set is considered as one point in the design space, which need to be further explored during the module selection step. Then during the module selection phase, the methodology systematically explores several combinations of hardware resource configurations (modules configuration set) that are satisfying time constraints and reports the optimal set with a minimum design area to the designer. Finally, clock cycle exploration step is guided automatically by the delays of modules of the configuration set.

English abstract

This paper describes a design exploration methodology that includes scheduling, module selection and clock cycle determination. The underlying methodology is constructed from one preliminary step and three main phases that allow improving every phase independently from the others without affecting their results, as well as it allows incorporation of the proposed techniques in any high-level synthesis system. The method starts by resource-constrained scheduling algorithm, which incorporates a local exploration mechanism to explore the design points so that each change in the resource set is considered as one point in the design space, which need to be further explored during the module selection step. Then during the module selection phase, the methodology systematically explores several combinations of hardware resource configurations (modules configuration set) that are satisfying time constraints and reports the optimal set with a minimum design area to the designer. Finally, clock cycle exploration step is guided automatically by the delays of modules of the configuration set.

Keywords

High-Level Synthesis, scheduling, Design space exploration

RIV year

2002

Released

25.04.2002

Location

Ostrava

ISBN

80-85988-71-2

Book

Proceedings of 36th International Conference MOSIS '02 Modelling and Simulation of Systems

Edition

Vol. I

Pages from

305

Pages to

312

Pages count

8

Documents

BibTex


@inproceedings{BUT10003,
  author="Azeddien {Sllame M.} and Vladimír {Drábek}",
  title="A Design Space Exploration Scheme for High-Level Synthesis Systems",
  annote="This paper describes a design exploration methodology that includes scheduling, module selection and clock cycle determination. The underlying methodology is constructed from one preliminary step and three main phases that allow improving every phase independently from the others without affecting their results, as well as it allows incorporation of the proposed techniques in any high-level synthesis system. The method starts by resource-constrained scheduling algorithm, which incorporates a local exploration mechanism to explore the design points so that each change in the resource set is considered as one point in the design space, which need to be further explored during the module selection step. Then during the module selection phase, the methodology systematically explores several combinations of hardware resource configurations (modules configuration set) that are satisfying time constraints and reports the optimal set with a minimum design area to the designer. Finally, clock cycle exploration step is guided automatically by the delays of modules of the configuration set.",
  booktitle="Proceedings of 36th International Conference MOSIS '02 Modelling and Simulation of Systems",
  chapter="10003",
  edition="Vol. I",
  year="2002",
  month="april",
  pages="305--312",
  type="conference paper"
}