Detail publikace

A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology

Originální název

A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology

Anglický název

A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology

Jazyk

en

Originální abstrakt

The presented work deals with design of the sigma-delta modulator in CMOS I2100 0,7 um technology. This modulator is designed using the switched capacitor technique (SC). For offset compensation of operational amplifiers (opamps) each integrator uses correlated double sampling technique (CDS), which minimize impact of offset of opamps. The sigma-delta modulator is part of the system for signal processing from sensor applications. Requirements for this converter were resolution 12-bits, voltage range 4 V, common mode voltage 2,5 V, +- 2 V input signal amplitude, bandwidth of a processed signal 5 kHz. Second order structure CIDIDF (Cascaded Integrator with Distributed Input and Distributed Feedback) was chosen.

Anglický abstrakt

The presented work deals with design of the sigma-delta modulator in CMOS I2100 0,7 um technology. This modulator is designed using the switched capacitor technique (SC). For offset compensation of operational amplifiers (opamps) each integrator uses correlated double sampling technique (CDS), which minimize impact of offset of opamps. The sigma-delta modulator is part of the system for signal processing from sensor applications. Requirements for this converter were resolution 12-bits, voltage range 4 V, common mode voltage 2,5 V, +- 2 V input signal amplitude, bandwidth of a processed signal 5 kHz. Second order structure CIDIDF (Cascaded Integrator with Distributed Input and Distributed Feedback) was chosen.

BibTex


@inproceedings{BUT93602,
  author="Vilém {Kledrowetz} and Michal {Pavlík} and Jiří {Háze} and Lukáš {Fujcik} and Roman {Prokop}",
  title="A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology",
  annote="The presented work deals with design of the sigma-delta modulator in CMOS I2100 0,7 um technology. This modulator is designed using the switched capacitor technique (SC). For offset compensation of operational amplifiers (opamps) each integrator uses correlated double sampling technique (CDS), which minimize impact of offset of opamps. The sigma-delta modulator is part of the system for signal processing from sensor applications. Requirements for this converter were resolution 12-bits, voltage range 4 V, common mode voltage 2,5 V, +- 2 V input signal amplitude, bandwidth of a processed signal 5 kHz. Second order structure CIDIDF (Cascaded Integrator with Distributed Input and Distributed Feedback) was chosen.",
  address="VUT Brno",
  booktitle="IMAPS CS International Conference 2012",
  chapter="93602",
  edition="1",
  howpublished="print",
  institution="VUT Brno",
  year="2012",
  month="june",
  pages="208--213",
  publisher="VUT Brno",
  type="conference paper"
}