Detail publikace

Digital Signal Soft-Processor for Audio and Video Processing

Originální název

Digital Signal Soft-Processor for Audio and Video Processing

Anglický název

Digital Signal Soft-Processor for Audio and Video Processing

Jazyk

en

Originální abstrakt

The paper presents a digital signal soft-processor DVSP that was designed using architecture description language ISAC by a tool for processor design called Lissom. First, a basic version of the processor with simple RISC instruction set was designed. Then, based on the target audio and video-processing applications, several instruction set extensions were added. Architecture of the designed processor is described in this paper. Processor was synthesized for several Xilinx FPGAs and synthesis and performance results are presented.

Anglický abstrakt

The paper presents a digital signal soft-processor DVSP that was designed using architecture description language ISAC by a tool for processor design called Lissom. First, a basic version of the processor with simple RISC instruction set was designed. Then, based on the target audio and video-processing applications, several instruction set extensions were added. Architecture of the designed processor is described in this paper. Processor was synthesized for several Xilinx FPGAs and synthesis and performance results are presented.

BibTex 


@article{BUT75630,
  author="Marián {Pristach} and Adam {Husár} and Lukáš {Fujcik} and Tomáš {Hruška} and Karel {Masařík}",
  title="Digital Signal Soft-Processor for Audio and Video Processing",
  annote="The paper presents a digital signal soft-processor DVSP that was designed using architecture description language ISAC by a tool for processor design called Lissom. First, a basic version of the processor with simple RISC instruction set was designed. Then, based on the target audio and video-processing applications, several instruction set extensions were added. Architecture of the designed processor is described in this paper. Processor was synthesized for several Xilinx FPGAs and synthesis and performance results are presented.",
  address="Západočeská univerzita v Plzni",
  chapter="75630",
  institution="Západočeská univerzita v Plzni",
  number="4",
  volume="2011",
  year="2011",
  month="june",
  pages="1--5",
  publisher="Západočeská univerzita v Plzni",
  type="journal article - other"
}