Detail publikace

Statistical Model of Blind-Oversampling Data Recovery with Probabilistic Domain Selection

Originální název

Statistical Model of Blind-Oversampling Data Recovery with Probabilistic Domain Selection

Anglický název

Statistical Model of Blind-Oversampling Data Recovery with Probabilistic Domain Selection

Jazyk

en

Originální abstrakt

The paper deals with a simulation model for a newly proposed feedforward blind oversampling Clock and Data Recovery circuit with low hardware complexity, which makes a new decision on the optimum sampling phase whenever a certain number of consecutive edges on the received data signal belong to the same sampling domain. The process of sampling domain selection can be represented by a Markov chain. The averaged Bit-Error Rate can be simply computed from the steady-state of the chain. Computational complexity is determined by the jitter period length. The model includes random and sinusoidal jitter and frequency offset of transmit and receive clocks.

Anglický abstrakt

The paper deals with a simulation model for a newly proposed feedforward blind oversampling Clock and Data Recovery circuit with low hardware complexity, which makes a new decision on the optimum sampling phase whenever a certain number of consecutive edges on the received data signal belong to the same sampling domain. The process of sampling domain selection can be represented by a Markov chain. The averaged Bit-Error Rate can be simply computed from the steady-state of the chain. Computational complexity is determined by the jitter period length. The model includes random and sinusoidal jitter and frequency offset of transmit and receive clocks.

BibTex


@inproceedings{BUT74700,
  author="Zdeněk {Kolka} and Michal {Kubíček} and Dalibor {Biolek} and Viera {Biolková} and Václav {Zeman}",
  title="Statistical Model of Blind-Oversampling Data Recovery with Probabilistic Domain Selection",
  annote="The paper deals with a simulation model for a newly proposed feedforward blind oversampling Clock and Data Recovery circuit with low hardware complexity, which makes a new decision on the optimum sampling phase whenever a certain number of consecutive edges on the received data
signal belong to the same sampling domain. The process of sampling domain selection can be represented by a Markov chain. The averaged Bit-Error Rate can be simply computed from the steady-state of the chain. Computational complexity is determined by the jitter period length. The model includes random and sinusoidal jitter and frequency offset of transmit and receive clocks.",
  address="AFCEA",
  booktitle="Proceedings of the 6th International Scientific Conference Communication and Information Technologies 2011",
  chapter="74700",
  howpublished="electronic, physical medium",
  institution="AFCEA",
  year="2011",
  month="october",
  pages="1--6",
  publisher="AFCEA",
  type="conference paper"
}