Detail publikace

Utilizing the Bulk-driven Technique in Low-voltage Low-power Integrated Circuits Design

Originální název

Utilizing the Bulk-driven Technique in Low-voltage Low-power Integrated Circuits Design

Anglický název

Utilizing the Bulk-driven Technique in Low-voltage Low-power Integrated Circuits Design

Jazyk

en

Originální abstrakt

Low-voltage (LV) and low-power (LP) consumption is a desirable feature for portable devices aiming at longer the battery life, prevent chips overheating, shrinking the battery size and its weight as well. Battery lifetime is a significant issue in all portable devices like mobile phones, laptops, portable and implantable medical devices, etc. Furthermore, the designers aim to have more and more battery-less portable devices where the battery cells are replaced by an alternative one, for example the photovoltaic cells. However, the future design should be ultra LV LP to increase the battery life. To achieve LV LP consumption of the portable devices all electronic circuits should be designed to operate under LV LP condition. Nowadays, the conceptions of low-voltage and ultra low-voltage are used for circuits which are able to run on supply voltages somewhere below 5V and 1V respectively. Therefore, this thesis presents an overview of current status and trends of the circuit techniques dedicated to design reliable LV LP analog circuit blocks. For considerations regarding: technology accessibility and price, design simplicity and power consumption the Bulk-driven technique has been chosen in this thesis to design several novel LV LP CMOS analog circuit blocks that utilize the bulk-terminal of the MOS transistor (MOST) as a signal port. This technique is used to avoid the threshold voltage requirements of the MOSTs, to achieve LV LP operation and acceptable circuit performance. Principle of the Bulk-driven MOST is described and critical design considerations are discussed. In the aim to enhance the performances of the proposed Bulk-driven circuits the self-cascode structure in the combination with the Bulk-driven technique are first used here in this thesis. The self-cascode structure increases the performances of the circuits furthermore it is very suitable for LV circuit design. This work also discusses and analyses in detail all the circuit parts necessary to realize low-voltage low-power MOST building blocks such as Bulk-driven current mirror, enhanced Bulk-driven current mirror, two stage Bulk-driven operation transconductance amplifiers (BD-OTA), novel mirrored cascode Bulk-driven OTA, novel Bulk-driven folded cascade OTA, rail-to-rail Bulk-driven OTA, novel Bulk-driven current conveyors (BD-CCII), novel enhanced Bulk-driven current conveyors and novel Bulk-driven current differencing transconductance amplifier (BD-CDTA). All mentioned Bulk-driven circuits are very well suited to LV LP and ultra LV LP environments. The voltage supplies used in Bulk-driven circuits design are in range of [+-0.6 V to +-0.3 V] with total power consumption in range of [200 uW to 10 uW], that is considered as ultra LV LP design. Also, suitable applications were chosen and applied on these blocks to show their proper functionalities. The simulations of the designed circuits were provided by OrCAD PSpice simulator, using TSMC 0.18 um CMOS process.

Anglický abstrakt

Low-voltage (LV) and low-power (LP) consumption is a desirable feature for portable devices aiming at longer the battery life, prevent chips overheating, shrinking the battery size and its weight as well. Battery lifetime is a significant issue in all portable devices like mobile phones, laptops, portable and implantable medical devices, etc. Furthermore, the designers aim to have more and more battery-less portable devices where the battery cells are replaced by an alternative one, for example the photovoltaic cells. However, the future design should be ultra LV LP to increase the battery life. To achieve LV LP consumption of the portable devices all electronic circuits should be designed to operate under LV LP condition. Nowadays, the conceptions of low-voltage and ultra low-voltage are used for circuits which are able to run on supply voltages somewhere below 5V and 1V respectively. Therefore, this thesis presents an overview of current status and trends of the circuit techniques dedicated to design reliable LV LP analog circuit blocks. For considerations regarding: technology accessibility and price, design simplicity and power consumption the Bulk-driven technique has been chosen in this thesis to design several novel LV LP CMOS analog circuit blocks that utilize the bulk-terminal of the MOS transistor (MOST) as a signal port. This technique is used to avoid the threshold voltage requirements of the MOSTs, to achieve LV LP operation and acceptable circuit performance. Principle of the Bulk-driven MOST is described and critical design considerations are discussed. In the aim to enhance the performances of the proposed Bulk-driven circuits the self-cascode structure in the combination with the Bulk-driven technique are first used here in this thesis. The self-cascode structure increases the performances of the circuits furthermore it is very suitable for LV circuit design. This work also discusses and analyses in detail all the circuit parts necessary to realize low-voltage low-power MOST building blocks such as Bulk-driven current mirror, enhanced Bulk-driven current mirror, two stage Bulk-driven operation transconductance amplifiers (BD-OTA), novel mirrored cascode Bulk-driven OTA, novel Bulk-driven folded cascade OTA, rail-to-rail Bulk-driven OTA, novel Bulk-driven current conveyors (BD-CCII), novel enhanced Bulk-driven current conveyors and novel Bulk-driven current differencing transconductance amplifier (BD-CDTA). All mentioned Bulk-driven circuits are very well suited to LV LP and ultra LV LP environments. The voltage supplies used in Bulk-driven circuits design are in range of [+-0.6 V to +-0.3 V] with total power consumption in range of [200 uW to 10 uW], that is considered as ultra LV LP design. Also, suitable applications were chosen and applied on these blocks to show their proper functionalities. The simulations of the designed circuits were provided by OrCAD PSpice simulator, using TSMC 0.18 um CMOS process.

BibTex


@misc{BUT68499,
  author="Fabian {Khateb}",
  title="Utilizing the Bulk-driven Technique in Low-voltage Low-power Integrated Circuits Design",
  annote="Low-voltage (LV) and low-power (LP) consumption is a desirable feature for portable devices aiming at longer the battery life, prevent chips overheating, shrinking the battery size and its weight as well. Battery lifetime is a significant issue in all portable devices like mobile phones, laptops, portable and implantable medical devices, etc. Furthermore, the designers aim to have more and more battery-less portable devices where the battery cells are replaced by an alternative one, for example the photovoltaic cells. However, the future design should be ultra LV LP to increase the battery life. To achieve LV LP consumption of the portable devices all electronic circuits should be designed to operate under LV LP condition.  
Nowadays, the conceptions of low-voltage and ultra low-voltage are used for circuits which are able to run on supply voltages somewhere below 5V and 1V respectively. Therefore, this thesis presents an overview of current status and trends of the circuit techniques dedicated to design reliable LV LP analog circuit blocks. For considerations regarding: technology accessibility and price, design simplicity and power consumption the Bulk-driven technique has been chosen in this thesis to design several novel LV LP CMOS analog circuit blocks that utilize the bulk-terminal of the MOS transistor (MOST) as a signal port. This technique is used to avoid the threshold voltage requirements of the MOSTs, to achieve LV LP operation and acceptable circuit performance. Principle of the Bulk-driven MOST is described and critical design considerations are discussed. In the aim to enhance the performances of the proposed Bulk-driven circuits the self-cascode structure in the combination with the Bulk-driven technique are first used here in this thesis. The self-cascode structure increases the performances of the circuits furthermore it is very suitable for LV circuit design. This work also discusses and analyses in detail all the circuit parts necessary to realize low-voltage low-power MOST building blocks such as Bulk-driven current mirror, enhanced Bulk-driven current mirror, two stage Bulk-driven operation transconductance amplifiers (BD-OTA), novel mirrored cascode Bulk-driven OTA, novel Bulk-driven folded cascade OTA, rail-to-rail Bulk-driven OTA, novel Bulk-driven current conveyors (BD-CCII), novel enhanced Bulk-driven current conveyors and novel Bulk-driven current differencing transconductance amplifier (BD-CDTA). All mentioned Bulk-driven circuits are very well suited to LV LP and ultra LV LP environments. The voltage supplies used in Bulk-driven circuits design are in range of [+-0.6 V to +-0.3 V] with total power consumption in range of [200 uW to 10 uW], that is considered as ultra LV LP design. Also, suitable applications were chosen and applied on these blocks to show their proper functionalities. The simulations of the designed circuits were provided by OrCAD PSpice simulator, using TSMC 0.18 um CMOS process.",
  address="VUTIUM",
  chapter="68499",
  institution="VUTIUM",
  year="2011",
  month="march",
  pages="1--36",
  publisher="VUTIUM",
  type="habilitation thesis"
}