Detail publikace

Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration

Originální název

Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration

Anglický název

Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration

Jazyk

en

Originální abstrakt

The article presents new background calibration technique, which is utilized in new 10-bit low power switched-capacitor(SC) pipelined ADC. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational amplifier (op-amp) sharing technique, shared operational transconductance amplifier (OTA) was used to decrease the power usage as well as capacitor scaling approach. The problems caused by SC (i.e. clock feedthrough from digital part through the switches, capacitor mismatch etc.) are avoided using the fully differential circuitry in conjunction with novel background calibration. The special OTAs and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the OTAs was taken into account too. The finite OTA dc gain problem is solved in digitaldomain using background calibration. The capacitor mismatch and OTA offset are compensated in the same manner as mentioned above.

Anglický abstrakt

The article presents new background calibration technique, which is utilized in new 10-bit low power switched-capacitor(SC) pipelined ADC. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational amplifier (op-amp) sharing technique, shared operational transconductance amplifier (OTA) was used to decrease the power usage as well as capacitor scaling approach. The problems caused by SC (i.e. clock feedthrough from digital part through the switches, capacitor mismatch etc.) are avoided using the fully differential circuitry in conjunction with novel background calibration. The special OTAs and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the OTAs was taken into account too. The finite OTA dc gain problem is solved in digitaldomain using background calibration. The capacitor mismatch and OTA offset are compensated in the same manner as mentioned above.

BibTex


@inproceedings{BUT18357,
  author="Jiří {Háze} and Radimír {Vrba} and Lukáš {Fujcik} and Ondřej {Sajdl}",
  title="Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration",
  annote="The article presents new background calibration technique, which is utilized in new 10-bit low power switched-capacitor(SC) pipelined ADC. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational amplifier (op-amp) sharing technique, shared operational transconductance amplifier (OTA) was used to decrease the power usage as well as capacitor scaling approach. The problems caused by SC (i.e. clock
feedthrough from digital part through the switches,
capacitor mismatch etc.) are avoided using the fully
differential circuitry in conjunction with novel
background calibration. The special OTAs and
comparators were designed for this purpose and to obtain
large bandwidth. The power consumption of the OTAs
was taken into account too.
The finite OTA dc gain problem is solved in digitaldomain
using background calibration. The capacitor
mismatch and OTA offset are compensated in the same
manner as mentioned above.",
  address="IEEE",
  booktitle="Proceedings of ICN 2006, ICONS 2006, MCL 2006",
  chapter="18357",
  institution="IEEE",
  year="2006",
  month="january",
  pages="116",
  publisher="IEEE",
  type="conference paper"
}