Detail publikace

Design of decimation filter for novel Sigma-Delta modulator

Originální název

Design of decimation filter for novel Sigma-Delta modulator

Anglický název

Design of decimation filter for novel Sigma-Delta modulator

Jazyk

en

Originální abstrakt

This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology.

Anglický abstrakt

This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology.

BibTex


@inproceedings{BUT15924,
  author="Lukáš {Fujcik} and Thibault {Mougel}",
  title="Design of decimation filter for novel Sigma-Delta modulator",
  annote="This paper describes steps involved in a new
VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values.
Finally, by analyzing the design, we can find an
efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology.",
  address="Technical University of Sofia",
  booktitle="THE FOURTEENT INTERNATIONAL SCIENTIFIC AND APPLIED SCIENCE CONFERENCE - ELECTRONICS ET'2005",
  chapter="15924",
  institution="Technical University of Sofia",
  year="2005",
  month="january",
  pages="58",
  publisher="Technical University of Sofia",
  type="conference paper"
}