Detail publikace

A 12-BIT LOW POWER SC PIPELINED ADC USING NOVEL BACKGROUND CALIBRATION APPROACH

Originální název

A 12-BIT LOW POWER SC PIPELINED ADC USING NOVEL BACKGROUND CALIBRATION APPROACH

Anglický název

A 12-BIT LOW POWER SC PIPELINED ADC USING NOVEL BACKGROUND CALIBRATION APPROACH

Jazyk

en

Originální abstrakt

The paper deals with a novel 12-bit low power switchedcapacitor (SC) pipelined analog-to-digital converter (ADC). The problems caused by using of SC technique are compensated or roughly attenuated by means of combination of well-known analog-domain techniques and new digital background calibration technique. Since portable applications demand for low power consumption, it is one of the most important issues onsidered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches the fully differential circuitry was utilized. The special op-amps and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the op-amps was taken into account too. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.

Anglický abstrakt

The paper deals with a novel 12-bit low power switchedcapacitor (SC) pipelined analog-to-digital converter (ADC). The problems caused by using of SC technique are compensated or roughly attenuated by means of combination of well-known analog-domain techniques and new digital background calibration technique. Since portable applications demand for low power consumption, it is one of the most important issues onsidered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches the fully differential circuitry was utilized. The special op-amps and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the op-amps was taken into account too. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.

BibTex


@inproceedings{BUT14984,
  author="Jiří {Háze} and Radimír {Vrba} and Lukáš {Fujcik} and Ondřej {Sajdl} and Michal {Skočdopole}",
  title="A 12-BIT LOW POWER SC PIPELINED ADC USING NOVEL BACKGROUND CALIBRATION APPROACH",
  annote="The paper deals with a novel 12-bit low power switchedcapacitor (SC) pipelined analog-to-digital converter (ADC). The problems caused by using of SC technique are compensated or roughly attenuated by means of combination of well-known analog-domain techniques and new digital background calibration technique.
Since portable applications demand for low power consumption, it is one of the most important issues onsidered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches the fully differential circuitry was utilized. The special op-amps and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the op-amps was taken into account too. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.",
  address="IEE",
  booktitle="Proceedings of the 5th IEE International Conference on ADDA 2005",
  chapter="14984",
  institution="IEE",
  year="2005",
  month="january",
  pages="283",
  publisher="IEE",
  type="conference paper"
}