Detail publikace

Reduction of the transistor mismaches effects in SI circuits

Originální název

Reduction of the transistor mismaches effects in SI circuits

Anglický název

Reduction of the transistor mismaches effects in SI circuits

Jazyk

en

Originální abstrakt

The switched current (SI) circuits with reduced effect of transistor mismatches are introduced. Elimination of this phenomenon is achieved by a modification of an already known SI basic unit-delay cell, in such a way that the number of required current mirror circuits is reduced. These cells can be used as a building block of any arbitrary sampled-data transfer function. As an example, a SI bilinear integrator circuit was designed.

Anglický abstrakt

The switched current (SI) circuits with reduced effect of transistor mismatches are introduced. Elimination of this phenomenon is achieved by a modification of an already known SI basic unit-delay cell, in such a way that the number of required current mirror circuits is reduced. These cells can be used as a building block of any arbitrary sampled-data transfer function. As an example, a SI bilinear integrator circuit was designed.

BibTex


@inproceedings{BUT11863,
  author="Roman {Prokop} and Vladislav {Musil} and Jiří {Stehlík}",
  title="Reduction of the transistor mismaches effects in SI circuits",
  annote="The switched current (SI) circuits with reduced effect of transistor mismatches are introduced. Elimination of this phenomenon is achieved by a modification of an already known SI basic unit-delay cell, in such a way that the number of required current mirror circuits is reduced. These cells can be used as a building block of any arbitrary sampled-data transfer function. As an example, a SI bilinear integrator circuit was designed.",
  address="Zd. Novotný",
  booktitle="Proceedings of the Socrates Workshop 2004",
  chapter="11863",
  institution="Zd. Novotný",
  year="2004",
  month="september",
  pages="145",
  publisher="Zd. Novotný",
  type="conference paper"
}