Detail publikace

Design of the 16bit (delta-sigma) Converter for Sensor Signal Processing

Originální název

Design of the 16bit (delta-sigma) Converter for Sensor Signal Processing

Anglický název

Design of the 16bit (delta-sigma) Converter for Sensor Signal Processing

Jazyk

en

Originální abstrakt

The paper deals with a design of the 16-bit MASH Delta-sigma converter utilizing switched capacitor technique (SC). The attention was paid to reach 16bit of ENOB resolution even the same precision of STF in band. This requirement is crucial to evaluation of the signal amplitude independently on its frequency. Multistage structure of two second order CIDIDF modulator was used. The system consists of continuous time amplifier, switched Delta-sigma modulator and decimation digital filter. The ONSemi I3T25 350nm CMOS technology was used for the design. The value of SNDR = 106.5 dB (ENOB = 17.4 bits) was achieved.

Anglický abstrakt

The paper deals with a design of the 16-bit MASH Delta-sigma converter utilizing switched capacitor technique (SC). The attention was paid to reach 16bit of ENOB resolution even the same precision of STF in band. This requirement is crucial to evaluation of the signal amplitude independently on its frequency. Multistage structure of two second order CIDIDF modulator was used. The system consists of continuous time amplifier, switched Delta-sigma modulator and decimation digital filter. The ONSemi I3T25 350nm CMOS technology was used for the design. The value of SNDR = 106.5 dB (ENOB = 17.4 bits) was achieved.

BibTex


@inproceedings{BUT111748,
  author="Michal {Pavlík} and Vilém {Kledrowetz} and Marián {Pristach} and Marek {Bohrn} and Lukáš {Fujcik} and Jiří {Háze}",
  title="Design of the 16bit (delta-sigma) Converter for Sensor Signal Processing",
  annote="The paper deals with a design of the 16-bit MASH Delta-sigma converter utilizing switched capacitor technique (SC). The attention was paid to reach 16bit of ENOB resolution even the same precision of STF in band. This requirement is crucial to evaluation of the signal amplitude independently on its frequency. Multistage structure of two second order CIDIDF modulator was used. The system consists of continuous time amplifier, switched Delta-sigma modulator and decimation digital filter. The ONSemi I3T25 350nm CMOS technology was used for the design. The value of SNDR = 106.5 dB (ENOB = 17.4 bits) was achieved.",
  booktitle="37th Internation Conference on Telecommunications and Signal Processing",
  chapter="111748",
  howpublished="electronic, physical medium",
  year="2014",
  month="july",
  pages="100--104",
  type="conference paper"
}