Detail publikace

Optimized Architecture of High Order CIC Filters

Originální název

Optimized Architecture of High Order CIC Filters

Anglický název

Optimized Architecture of High Order CIC Filters

Jazyk

en

Originální abstrakt

The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The main advantages of the architecture are higher working frequency, smaller area size and lower power consumption. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

Anglický abstrakt

The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The main advantages of the architecture are higher working frequency, smaller area size and lower power consumption. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

BibTex


@inproceedings{BUT100993,
  author="Marián {Pristach} and Michal {Pavlík} and Jiří {Háze} and Lukáš {Fujcik}",
  title="Optimized Architecture of High Order CIC Filters",
  annote="The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The main advantages of the architecture are higher working frequency, smaller area size and lower power consumption. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.",
  address="Lodz University of Technology",
  booktitle="Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems",
  chapter="100993",
  howpublished="electronic, physical medium",
  institution="Lodz University of Technology",
  year="2013",
  month="june",
  pages="263--266",
  publisher="Lodz University of Technology",
  type="conference paper"
}