Detail publikace

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

KAŠTIL, J. STRAKA, M. MIČULKA, L. KOTÁSEK, Z.

Originální název

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Anglický název

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Jazyk

en

Originální abstrakt

In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on redundancy of functional units associated with a concurrent error detection technique and it uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture the Markov dependability models are created and it is demonstrated how the reliability and availability parameters are derived from this model for different configurations of architectures and faulty modules. The reliability analysis results are shown.

Anglický abstrakt

In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on redundancy of functional units associated with a concurrent error detection technique and it uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture the Markov dependability models are created and it is demonstrated how the reliability and availability parameters are derived from this model for different configurations of architectures and faulty modules. The reliability analysis results are shown.

Dokumenty

BibTex


@inproceedings{BUT96980,
  author="Jan {Kaštil} and Martin {Straka} and Lukáš {Mičulka} and Zdeněk {Kotásek}",
  title="Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA",
  annote="In this paper, a dependability analysis of fault tolerant systems implemented
into the SRAM-based FPGA is presented. The fault tolerant architectures are based
on redundancy of functional units associated with a concurrent error detection
technique and it uses the principles of partial dynamic reconfiguration as
a recovery mechanism from a fault occurrence. Architectures are tested by
injecting soft errors into partial bitstream in FPGA by SEU injector and the
faults coverage of this architecture is obtained. From faults coverage, the
failure rate and repair rate are evaluated. Then, for fault tolerant architecture
the Markov dependability models are created and it is demonstrated how the
reliability and availability parameters are derived from this model for different
configurations of architectures and faulty modules. The reliability analysis
results are shown.",
  address="IEEE Computer Society",
  booktitle="15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools",
  chapter="96980",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2012",
  month="may",
  pages="250--257",
  publisher="IEEE Computer Society",
  type="conference paper"
}