Detail publikace

A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems

OTERO, A. SALVADOR, R. MORA, J. DE LA TORRE, E. RIESGO, T. SEKANINA, L.

Originální název

A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems

Anglický název

A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems

Jazyk

en

Originální abstrakt

Modern FPGAs with Dynamic and Partial Reconfiguration (DPR) features allow the implementation of complex, yet flexible, hardware systems. Combining this flexibility with evolvable hardware techniques, real adaptive systems, able to reconfigure themselves according to environmental changes, can be envisaged. In this paper, a highly regular and modular architecture combined with a fast reconfiguration mechanism is proposed, allowing the introduction of dynamic and partial reconfiguration in the evolvable hardware loop. Results and use case show that, following this approach, evolvable processing IP Cores can be built, providing intensive data processing capabilities, improving data and delay overheads with respect to previous proposals. Results also show that, in the worst case (maximum mutation rate), average reconfiguration time is 5 times lower than evaluation time.

Anglický abstrakt

Modern FPGAs with Dynamic and Partial Reconfiguration (DPR) features allow the implementation of complex, yet flexible, hardware systems. Combining this flexibility with evolvable hardware techniques, real adaptive systems, able to reconfigure themselves according to environmental changes, can be envisaged. In this paper, a highly regular and modular architecture combined with a fast reconfiguration mechanism is proposed, allowing the introduction of dynamic and partial reconfiguration in the evolvable hardware loop. Results and use case show that, following this approach, evolvable processing IP Cores can be built, providing intensive data processing capabilities, improving data and delay overheads with respect to previous proposals. Results also show that, in the worst case (maximum mutation rate), average reconfiguration time is 5 times lower than evaluation time.

Dokumenty

BibTex


@inproceedings{BUT76399,
  author="Andres {Otero} and Ruben {Salvador} and Javier {Mora} and Eduardo {De la Torre} and Teresa {Riesgo} and Lukáš {Sekanina}",
  title="A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems",
  annote="Modern FPGAs with Dynamic and Partial Reconfiguration (DPR) features allow the
implementation of complex, yet flexible, hardware systems. Combining this
flexibility with evolvable hardware techniques, real adaptive systems, able to
reconfigure themselves according to environmental changes, can be envisaged. In
this paper, a highly regular and modular architecture combined with a fast
reconfiguration mechanism is proposed, allowing the introduction of dynamic and
partial reconfiguration in the evolvable hardware loop. Results and use case show
that, following this approach, evolvable processing IP Cores can be built,
providing intensive data processing capabilities, improving data and delay
overheads with respect to previous proposals. Results also show that, in the
worst case (maximum mutation rate), average reconfiguration time is 5 times lower
than evaluation time.",
  address="IEEE Computer Society",
  booktitle="Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems",
  chapter="76399",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2011",
  month="june",
  pages="336--343",
  publisher="IEEE Computer Society",
  type="conference paper"
}