Detail publikace

Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads

STRNADEL, J.

Originální název

Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads

Anglický název

Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads

Jazyk

en

Originální abstrakt

In the paper, concept and early analysis of an embedded HW/SW architecture designed to prevent the SW from interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the HW (SW) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt to various interrupt rates according to the actual MCU load. The adaptation is possible because the HW is both informed about the actual SW load on basis of signals send from the SW to the HW and able to buffer all interrupts incomming to the MCU when the SW is highly loaded or redirect the interrupts to the MCU as soon as the SW becomes underloaded.

Anglický abstrakt

In the paper, concept and early analysis of an embedded HW/SW architecture designed to prevent the SW from interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the HW (SW) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt to various interrupt rates according to the actual MCU load. The adaptation is possible because the HW is both informed about the actual SW load on basis of signals send from the SW to the HW and able to buffer all interrupts incomming to the MCU when the SW is highly loaded or redirect the interrupts to the MCU as soon as the SW becomes underloaded.

Dokumenty

BibTex


@inproceedings{BUT76369,
  author="Josef {Strnadel}",
  title="Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads",
  annote="In the paper, concept and early analysis of an embedded HW/SW architecture
designed to prevent the SW from interrupt overloads is outlined. The architecture
is composed of an FPGA (MCU) used to run the HW (SW) part of an embedded
application. Comparing to previous approaches, novelty of the architecture can be
seen in the fact it is able to adapt to various interrupt rates according to the
actual MCU load. The adaptation is possible because the HW is both informed about
the actual SW load on basis of signals send from the SW to the HW and able to
buffer all interrupts incomming to the MCU when the SW is highly loaded or
redirect the interrupts to the MCU as soon as the SW becomes underloaded.",
  address="Johannes Kepler University Linz",
  booktitle="Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design",
  chapter="76369",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Johannes Kepler University Linz",
  year="2011",
  month="may",
  pages="21--22",
  publisher="Johannes Kepler University Linz",
  type="conference paper"
}