Detail publikace

Design and Simulation of High Performance Parallel Architectures Using the ISAC Language

Originální název

Design and Simulation of High Performance Parallel Architectures Using the ISAC Language

Anglický název

Design and Simulation of High Performance Parallel Architectures Using the ISAC Language

Jazyk

en

Originální abstrakt

Most of modern embedded systems for multimedia and network applications are based on parallel data stream processing. The data processing can be done using very long instruction word processors (VLIW), or using more than one high performance application-specific instruction set processor (ASIPs), or even by their combination on single chip. Design and testing of these complex systems is time-consuming and iterative process. Architecture description languages (ADLs) are one of the most effective solutions for single processor design. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in nowadays ADLs. This article presents utilization of new extensions for existing architecture description language ISAC. These extensions are used for easy and fast prototyping and testing of parallel based systems and processors. This article extends the previous publication on RTES 2010 conference.

Anglický abstrakt

Most of modern embedded systems for multimedia and network applications are based on parallel data stream processing. The data processing can be done using very long instruction word processors (VLIW), or using more than one high performance application-specific instruction set processor (ASIPs), or even by their combination on single chip. Design and testing of these complex systems is time-consuming and iterative process. Architecture description languages (ADLs) are one of the most effective solutions for single processor design. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in nowadays ADLs. This article presents utilization of new extensions for existing architecture description language ISAC. These extensions are used for easy and fast prototyping and testing of parallel based systems and processors. This article extends the previous publication on RTES 2010 conference.

BibTex


@article{BUT76296,
  author="Zdeněk {Přikryl} and Jakub {Křoustek} and Tomáš {Hruška} and Dušan {Kolář} and Karel {Masařík} and Adam {Husár}",
  title="Design and Simulation of High Performance Parallel Architectures Using the ISAC Language",
  annote="Most of modern embedded systems for multimedia and network applications are based
on parallel data stream processing. The data processing can be done using very
long instruction word processors (VLIW), or using more than one high performance
application-specific instruction set processor (ASIPs), or even by their
combination on single chip.

Design and testing of these complex systems is time-consuming and iterative
process. Architecture description languages (ADLs) are one of the most effective
solutions for single processor design. However, support for description of
parallel architectures and multi-processor systems is very low or completely
missing in nowadays ADLs. This article presents utilization of new extensions for
existing architecture description language ISAC. These extensions are used for
easy and fast prototyping and testing of parallel based systems and processors.

This article extends the previous publication on RTES 2010 conference.",
  address="Global Science & Technology Forum",
  booktitle="GSTF International Journal on Computing",
  chapter="76296",
  doi="10.5176/2010-2283_1.2.46",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Global Science & Technology Forum",
  number="2",
  volume="1",
  year="2011",
  month="february",
  pages="97--106",
  publisher="Global Science & Technology Forum",
  type="journal article - other"
}