Packet Triggered Architecture

Packet Triggered Architecture

článek ve sborníku ve WoS nebo Scopus

čeština

Nowadays, it is necessary a fast developing of applications with high efficiency and low power consumption. This is the basic reason to develop a configurable processor or accelerator, which can be adapted to target application with as minimal necessary hardware as possible for better power savings. Because in the least years the processors innovations is mostly based on old concepts as increase degree of parallelism (number of a parallel processed instructions and parallel cores), bather utilization of a memory interface and instruction/data stalls. Then we thing it is possible to develop a new approach to design processor/accelerator and the answer was yes it is. The answer for that question is called the Packet Triggered Architecture (PTA).

Nowadays, it is necessary a fast developing of applications with high efficiency and low power consumption. This is the basic reason to develop a configurable processor or accelerator, which can be adapted to target application with as minimal necessary hardware as possible for better power savings. Because in the least years the processors innovations is mostly based on old concepts as increase degree of parallelism (number of a parallel processed instructions and parallel cores), bather utilization of a memory interface and instruction/data stalls. Then we thing it is possible to develop a new approach to design processor/accelerator and the answer was yes it is. The answer for that question is called the Packet Triggered Architecture (PTA).

Network on Chip (NoC), configurable processor, accelerators.

Network on Chip (NoC), configurable processor, accelerators.

ADAMEC, F.

2011

22. 11. 2011

978-80-214-4368-6

Pokročilé metody, struktury a komponenty elektronické bezdrátové komunikace. Sborník semináře o řešení doktorského projektu Grantové agentury České republiky č. 102/08/H027 v roce 2011

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