Detail publikace

The Design of On-line Checkers and Their Use in Verification and Testing

Originální název

The Design of On-line Checkers and Their Use in Verification and Testing

Anglický název

The Design of On-line Checkers and Their Use in Verification and Testing

Jazyk

en

Originální abstrakt

In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. The results and compare of both methodologies are described. The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.

Anglický abstrakt

In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. The results and compare of both methodologies are described. The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.

BibTex


@article{BUT47975,
  author="Zdeněk {Kotásek} and Martin {Straka}",
  title="The Design of On-line Checkers and Their Use in Verification and Testing",
  annote="In the article, a survey of our research activities the goal of which is to
develop a methodology allowing to design on-line checkers for digital components
and communication protocols are described. First, our experiments with PSL
language and FoCs tool are demonstrated for simple RT circuits and communication
protocols. It is shown how PSL can be used to describe conditions to be checked
by an on-line checker of a digital component. It is demonstrated that on-line
checkers generated from PSL description demand more sources than the unit under
check which is seen as unacceptable result. The principle of our methodology for
generating VHDL descriptions of hardware checkers from the formal model is
presented, too. The results and compare of both methodologies are described. The
possibilities of utilizing these approaches in the design of Fault Tolerant
Systems are described in conclusion.",
  address="NEUVEDEN",
  chapter="47975",
  edition="NEUVEDEN",
  howpublished="print",
  institution="NEUVEDEN",
  journal="Acta Electrotechnica et Informatica",
  number="3",
  volume="2009",
  year="2009",
  month="september",
  pages="8--15",
  publisher="NEUVEDEN",
  type="journal article - other"
}