Detail publikace

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

Originální název

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

Anglický název

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

Jazyk

en

Originální abstrakt

In most of existing approaches, the reorganization of test vector sequence and reordering scan chains registers to reduce power consumption are solved separately, they are seen as independent procedures. In the paper it is shown that a  correlation between these two processes and strong reasons to combine them into one procedure run concurrently exist. Based on this idea, it is demonstrated that search spaces of both procedures can be combined together into a single search space in order to achieve better results during the optimization process. The optimization over the united search space was tested on ISCAS85, ISCAS89 and ITC99 benchmark circuits implemented by means of CMOS primitives from AMI technological libraries. Results presented in the paper show that lower power consumption can be achieved if the correlation is reflected, i.e., if the search space is united rather than divided into separate spaces. At the end of the paper, results achieved by genetic algorithm based optimization are presented, discussed and compared with results of existing methods.

Anglický abstrakt

In most of existing approaches, the reorganization of test vector sequence and reordering scan chains registers to reduce power consumption are solved separately, they are seen as independent procedures. In the paper it is shown that a  correlation between these two processes and strong reasons to combine them into one procedure run concurrently exist. Based on this idea, it is demonstrated that search spaces of both procedures can be combined together into a single search space in order to achieve better results during the optimization process. The optimization over the united search space was tested on ISCAS85, ISCAS89 and ITC99 benchmark circuits implemented by means of CMOS primitives from AMI technological libraries. Results presented in the paper show that lower power consumption can be achieved if the correlation is reflected, i.e., if the search space is united rather than divided into separate spaces. At the end of the paper, results achieved by genetic algorithm based optimization are presented, discussed and compared with results of existing methods.

BibTex


@inproceedings{BUT35934,
  author="Zdeněk {Kotásek} and Jaroslav {Škarvada} and Josef {Strnadel}",
  title="The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption",
  annote="In most of existing approaches, the reorganization of test vector sequence and
reordering scan chains registers to reduce power consumption are solved
separately, they are seen as independent procedures. In the paper it is shown
that a  correlation between these two processes and strong reasons to combine
them into one procedure run concurrently exist. Based on this idea, it is
demonstrated that search spaces of both procedures can be combined together into
a single search space in order to achieve better results during the optimization
process. The optimization over the united search space was tested on ISCAS85,
ISCAS89 and ITC99 benchmark circuits implemented by means of CMOS primitives from
AMI technological libraries. Results presented in the paper show that lower power
consumption can be achieved if the correlation is reflected, i.e., if the search
space is united rather than divided into separate spaces. At the end of the
paper, results achieved by genetic algorithm based optimization are presented,
discussed and compared with results of existing methods.",
  address="IEEE Computer Society",
  booktitle="Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools",
  chapter="35934",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2010",
  month="september",
  pages="644--651",
  publisher="IEEE Computer Society",
  type="conference paper"
}