Detail publikace

Generating Proper VLIW Assembler Code Using Scattered Context Grammars

Originální název

Generating Proper VLIW Assembler Code Using Scattered Context Grammars

Anglický název

Generating Proper VLIW Assembler Code Using Scattered Context Grammars

Jazyk

en

Originální abstrakt

The very long instruction word (VLIW) processor architecture is focused on~a~high instruction level parallelism. Program execution is scheduled statically at~compilation time. Therefore, there is no need for run-time scheduling and dependency checking mechanisms. On the other hand, all these constraints must be controlled by the compiler. This paper describes usage of scattered context grammars in order to model instruction level limitations of these processors. Resulting grammar generates proper assembler code. This concept has two advantages -- formal description of the dependency checking process and high reduction of production rules over other methods.

Anglický abstrakt

The very long instruction word (VLIW) processor architecture is focused on~a~high instruction level parallelism. Program execution is scheduled statically at~compilation time. Therefore, there is no need for run-time scheduling and dependency checking mechanisms. On the other hand, all these constraints must be controlled by the compiler. This paper describes usage of scattered context grammars in order to model instruction level limitations of these processors. Resulting grammar generates proper assembler code. This concept has two advantages -- formal description of the dependency checking process and high reduction of production rules over other methods.

BibTex


@inproceedings{BUT34656,
  author="Jakub {Křoustek} and Stanislav {Židek}",
  title="Generating Proper VLIW Assembler Code Using Scattered Context Grammars",
  annote="The very long instruction word (VLIW) processor architecture is focused on~a~high
instruction level parallelism. Program execution is scheduled statically
at~compilation time. Therefore, there is no need for run-time scheduling and
dependency checking mechanisms. On the other hand, all these constraints must be
controlled by the compiler. This paper describes usage of scattered context
grammars in order to model instruction level limitations of these processors.
Resulting grammar generates proper assembler code. This concept has two
advantages -- formal description of the dependency checking process and high
reduction of production rules over other methods.",
  address="Faculty of Information Technology BUT",
  booktitle="Proceedings of the 16th Conference Student EEICT 2010 Volume 5",
  chapter="34656",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Faculty of Information Technology BUT",
  year="2010",
  month="april",
  pages="181--185",
  publisher="Faculty of Information Technology BUT",
  type="conference paper"
}