Detail publikace

Packet Header Analysis and Field Extraction for Multigigabit Networks

Originální název

Packet Header Analysis and Field Extraction for Multigigabit Networks

Anglický název

Packet Header Analysis and Field Extraction for Multigigabit Networks

Jazyk

en

Originální abstrakt

Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing is required. We propose a new architecture of packet header analysis and fields extraction intended for high-speed FPGA-based network applications. The architecture is able to process 20 Gbps network links with less than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the presented solution can balance between network throughput and consumed hardware resources to fit application needs. The architecture for packet header processing is generated from standard XML protocol scheme and is strongly optimised for resource consumption and speed by an automatic HDL code   generator. Our solution also enables to change the set of extracted header fields on-line without FPGA reconfiguration.

Anglický abstrakt

Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing is required. We propose a new architecture of packet header analysis and fields extraction intended for high-speed FPGA-based network applications. The architecture is able to process 20 Gbps network links with less than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the presented solution can balance between network throughput and consumed hardware resources to fit application needs. The architecture for packet header processing is generated from standard XML protocol scheme and is strongly optimised for resource consumption and speed by an automatic HDL code   generator. Our solution also enables to change the set of extracted header fields on-line without FPGA reconfiguration.

BibTex


@inproceedings{BUT33781,
  author="Petr {Kobierský} and Jan {Kořenek} and Libor {Polčák}",
  title="Packet Header Analysis and Field Extraction for Multigigabit Networks",
  annote="Packet header analysis and extraction of header fields needs to be performed in
all network devices. As network speed is increasing quickly, high speed packet
header processing is required. We propose a new architecture of packet header
analysis and fields extraction intended for high-speed FPGA-based network
applications. The architecture is able to process 20 Gbps network links with less
than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the
presented solution can balance between network throughput and consumed hardware
resources to fit application needs. The architecture for packet header processing
is generated from standard XML protocol scheme and is strongly optimised for
resource consumption and speed by an automatic HDL code   generator. Our solution
also enables to change the set of extracted header fields on-line without FPGA
reconfiguration.",
  address="IEEE Computer Society",
  booktitle="Proceedings of the 2009 IEEE Symphosium on  Design and Diagnostics of Electronic Circuits and Systems",
  chapter="33781",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2009",
  month="april",
  pages="96--101",
  publisher="IEEE Computer Society",
  type="conference paper"
}