Detail publikace

Fast Cycle-Accurate Interpreted Simulation

Originální název

Fast Cycle-Accurate Interpreted Simulation

Anglický název

Fast Cycle-Accurate Interpreted Simulation

Jazyk

en

Originální abstrakt

The area of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria, such as power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hardware realization.

Anglický abstrakt

The area of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria, such as power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hardware realization.

BibTex


@inproceedings{BUT30917,
  author="Zdeněk {Přikryl} and Karel {Masařík} and Tomáš {Hruška} and Adam {Husár}",
  title="Fast Cycle-Accurate Interpreted Simulation",
  annote="The area of hardware/software co-design deals with the design of
ASIPs(Application Specific Instruction-set Processors) because they often create
the core of an embedded system. Embedded systems with ASIPs are designed for
a given task and they have to fulfill several criteria, such as power
consumption, chip size, etc. The success of the design phase is closely related
to the existence of good design tools, i.e. tools for ASIP programming and
simulation. The simulation itself is very important, because with it we can
verify and validate an ASIP design. For this purpose, ASIPs are described using
an architecture description language that allows generating the design tools in
an automatic way. In this article, we focus on presenting the principles which
are used in our fast cycle-accurate interpreted simulator. Beside the simulation
speed, we also focus on equivalence assurance between an ASIP simulator and its
hardware realization.",
  address="IEEE Computer Society Press",
  booktitle="Tenth International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions",
  chapter="30917",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society Press",
  year="2009",
  month="december",
  pages="9--14",
  publisher="IEEE Computer Society Press",
  type="conference paper"
}