Detail publikace

On Evolutionary Synthesis of Linear Transforms

Originální název

On Evolutionary Synthesis of Linear Transforms

Anglický název

On Evolutionary Synthesis of Linear Transforms

Jazyk

en

Originální abstrakt

In this paper, an evolutionary approach is used to design multiple constant multipliers (MCMs). As these circuits can be composed of adders, subtractors and shifters, they perform a linear transform. An important consequence is that only a single input value is sufficient to completely evaluate a candidate circuit independently of its size and the bit width of the datapath. Proposed method is able to compete with well-optimized heuristics in particular problem instances. This paper also deals with a hardware acceleration of the method in FPGA which provides the speedup of two orders of magnitude in comparison with a conventional PC.

Anglický abstrakt

In this paper, an evolutionary approach is used to design multiple constant multipliers (MCMs). As these circuits can be composed of adders, subtractors and shifters, they perform a linear transform. An important consequence is that only a single input value is sufficient to completely evaluate a candidate circuit independently of its size and the bit width of the datapath. Proposed method is able to compete with well-optimized heuristics in particular problem instances. This paper also deals with a hardware acceleration of the method in FPGA which provides the speedup of two orders of magnitude in comparison with a conventional PC.

BibTex


@inproceedings{BUT30901,
  author="Zdeněk {Vašíček} and Martin {Žádník} and Lukáš {Sekanina} and Jiří {Tobola}",
  title="On Evolutionary Synthesis of Linear Transforms",
  annote="In this paper, an evolutionary approach is used to design multiple constant
multipliers (MCMs). As these circuits can be composed
of adders, subtractors and shifters, they perform a linear transform. An
important consequence is that only a single input value is sufficient to
completely evaluate a candidate circuit independently of its size and the bit
width of the datapath. Proposed method is able to compete with well-optimized
heuristics in particular problem instances. This paper also deals with a hardware
acceleration of the method in FPGA which provides the speedup of two orders of
magnitude in comparison
with a conventional PC.",
  address="Springer Verlag",
  booktitle="Evolvable Systems: From Biology > to > Hardware",
  chapter="30901",
  edition="Lecture Notes in Computer Science",
  howpublished="print",
  institution="Springer Verlag",
  journal="Lecture Notes in Computer Science (IF 0,513)",
  year="2008",
  month="september",
  pages="141--152",
  publisher="Springer Verlag",
  type="conference paper"
}