Detail publikace

Design of Integer Phase Locked Loop

Originální název

Design of Integer Phase Locked Loop

Anglický název

Design of Integer Phase Locked Loop

Jazyk

en

Originální abstrakt

The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .

Anglický abstrakt

The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .

Dokumenty

BibTex


@inproceedings{BUT28635,
  author="Jiří {Háze} and Radimír {Vrba} and Lukáš {Fujcik} and Roman {Prokop}",
  title="Design of Integer Phase Locked Loop",
  annote="The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .",
  address="Novotný",
  booktitle="MIKROSYN. Nové trendy v mikroelektronických systémech a nanotechnologiích.. Seminář o výsledcích výzkumného záměru MSM 0021630503 v roce 2007. Sborník příspěvků",
  chapter="28635",
  institution="Novotný",
  year="2007",
  month="december",
  pages="27--34",
  publisher="Novotný",
  type="conference paper"
}