Detail publikace

RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool

Originální název

RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool

Anglický název

RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool

Jazyk

en

Originální abstrakt

The paper presents testability analysis method which is based on partitioning circuit under analysis (CUA) to testable blocks (TBs). A formal approach utilizing the concepts of discrete mathematics is used for this purpose. The partitioning CUA into TBs is further exploited for power consumption optimization during test application. Software tools which were developed during the research and integrated into the third party design tool are also described. Experimental results gained from applying the methodology on selected benchmarks and practical designs are demonstrated.

Anglický abstrakt

The paper presents testability analysis method which is based on partitioning circuit under analysis (CUA) to testable blocks (TBs). A formal approach utilizing the concepts of discrete mathematics is used for this purpose. The partitioning CUA into TBs is further exploited for power consumption optimization during test application. Software tools which were developed during the research and integrated into the third party design tool are also described. Experimental results gained from applying the methodology on selected benchmarks and practical designs are demonstrated.

BibTex


@inproceedings{BUT26071,
  author="Jaroslav {Škarvada} and Tomáš {Herrman} and Zdeněk {Kotásek}",
  title="RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool",
  annote="The paper presents testability analysis method which is based on partitioning
circuit under analysis (CUA) to testable blocks (TBs). A formal approach
utilizing the concepts of discrete mathematics is used for this purpose. The
partitioning CUA into TBs is further exploited for power consumption optimization
during test application. Software tools which were developed during the research
and integrated into the third party design tool are also described. Experimental
results gained from applying the methodology on selected benchmarks and practical
designs are demonstrated.",
  address="Institute of Computing Technology, Chinese Academy of Sciences",
  booktitle="IEEE 8th Workshop on RTL and High Level Testing",
  chapter="26071",
  howpublished="print",
  institution="Institute of Computing Technology, Chinese Academy of Sciences",
  year="2007",
  month="october",
  pages="175--181",
  publisher="Institute of Computing Technology, Chinese Academy of Sciences",
  type="conference paper"
}