Detail publikace

Checker for Communication Protocol between IP Cores Based on FPGA

STRAKA, M. KOTÁSEK, Z.

Originální název

Checker for Communication Protocol between IP Cores Based on FPGA

Anglický název

Checker for Communication Protocol between IP Cores Based on FPGA

Jazyk

en

Originální abstrakt

In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro FPGA was used for the implementation. Future research will be directed towards the development of fault tolerant systems design methodology in which the presented approach can be possibly used.

Anglický abstrakt

In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro FPGA was used for the implementation. Future research will be directed towards the development of fault tolerant systems design methodology in which the presented approach can be possibly used.

Dokumenty

BibTex


@inproceedings{BUT25345,
  author="Martin {Straka} and Zdeněk {Kotásek}",
  title="Checker for Communication Protocol between IP Cores Based on FPGA",
  annote="In the paper, the principles of a unit design which can be used for on-line
communication protocol checking is presented. It is shown how the checker can be
used to check the communication between IP cores implemented in FPGA. The
communication must be precisely defined - for this purpose, a formal approach was
developed which allows to describe ambiguously the conditions which must be
satisfied during the communication. From the description, the checker description
in VHDL is generated (a compiler was developed for this purpose) and implemented
into FPGA. The checker watches the communication and detects such states which do
not satisfy protocol definitions. If such a situation appears, it is indicated
that hardware implementation does not work properly. The methodology was verified
on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro FPGA was
used for the implementation. Future research will be directed towards the
development of fault tolerant systems
design methodology in which the presented approach can be possibly used.",
  address="Faculty of Informatics MU",
  booktitle="3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  chapter="25345",
  howpublished="print",
  institution="Faculty of Informatics MU",
  year="2007",
  month="october",
  pages="193--200",
  publisher="Faculty of Informatics MU",
  type="conference paper"
}