Detail publikace

New approach to the FPGA testing based on the Boundary Scan

KOTÁSEK, Z., TUPEC, P.

Originální název

New approach to the FPGA testing based on the Boundary Scan

Anglický název

New approach to the FPGA testing based on the Boundary Scan

Jazyk

en

Originální abstrakt

In the paper, a method enabling to verify the functionality of an FPGA design is presented. This method is based on the formal model construction of the register transfer (RT) level digital circuit. This new approach allows FPGA designers to debug and verify their hardware being developed. A Boundary scan is used as a communication interface. As an input, a digital circuit structure at RT level designed using any DfT technique is assumed.

Anglický abstrakt

In the paper, a method enabling to verify the functionality of an FPGA design is presented. This method is based on the formal model construction of the register transfer (RT) level digital circuit. This new approach allows FPGA designers to debug and verify their hardware being developed. A Boundary scan is used as a communication interface. As an input, a digital circuit structure at RT level designed using any DfT technique is assumed.

Dokumenty

BibTex


@inproceedings{BUT16896,
  author="Zdeněk {Kotásek} and Pavel {Tupec}",
  title="New approach to the FPGA testing based on the Boundary Scan",
  annote="In the paper, a method enabling to verify the functionality of an FPGA
design is presented. This method is based on the formal model
construction of the register transfer (RT) level digital circuit. This
new approach allows FPGA designers to debug and verify their hardware
being developed. A Boundary scan is used as a communication interface.
As an input, a digital circuit structure at RT level designed using any
DfT technique is assumed.",
  booktitle="Proceedings of 38th International Conference MOSIS'04",
  chapter="16896",
  year="2004",
  month="may",
  pages="120--123",
  type="conference paper"
}