Detail publikace

Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures

ŠŤÁVA, M.

Originální název

Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper presents a novel online fault tolerance method for network-on-chip (NoC) interconnects targeting both permanent and transient faults. We introduce a concept of retransmission credit as a method of distinguishing between permanent and transient faults. Another concept of monitoring errors separately on two types of interconnects – inter-switch links and intra-switch input/output port paths – is also employed. The concept introduced allows more efficient routing in comparison to existing error recovery schemes. Experimental validation shows that the proposed NoC error recovery scheme utilising both the concepts delivers better or at least similar performance when compared to existing NoC error recovery schemes.

Klíčová slova

fault tolerance, error recovery, network on chip, permanent or transient fault, performance

Autoři

ŠŤÁVA, M.

Vydáno

30. 5. 2019

Nakladatel

IEEE

ISBN

978-1-7281-0073-9

Kniha

22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019

ISSN

2473-2117

Periodikum

IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems

Stát

Spojené státy americké

Strany od

1

Strany do

4

Strany počet

4

BibTex

@inproceedings{BUT156411,
  author="Martin {Šťáva}",
  title="Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures",
  booktitle="22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019",
  year="2019",
  journal="IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems",
  pages="1--4",
  publisher="IEEE",
  doi="10.1109/DDECS.2019.8724641",
  isbn="978-1-7281-0073-9",
  issn="2473-2117"
}