Detail publikace

Reliability Analysis and Improvement of FPGA-based Robot Controller

PODIVÍNSKÝ, J. LOJDA, J. ČEKAN, O. PÁNEK, R. KOTÁSEK, Z.

Originální název

Reliability Analysis and Improvement of FPGA-based Robot Controller

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

Faults occurring in the safety-critical systems can lead to the failure of the whole system and can cause high economical losses or endanger human health. As an example space, aerospace or medical systems can serve which are working in the environment with increased occurrence of faults. Fault avoidance and fault tolerance are the main techniques the goal of which is to avoid such situations. This paper is the continuation of the previously published work and presents an approach to evaluation of the fault tolerance techniques by monitoring the impact of faults in the experimental electro-mechanical system which consists of the robot in maze and its robot controller. The experiments with the robot controller hardened against faults are combined with the reliability analysis on theoretical level in this paper. The impact of faults artificially injected into the robot controller, in which Triple Modular Redundancy is applied, is monitored and used for the statistic reliability analysis.

Klíčová slova

Reliability Analysis TMR FPGA Fault Tolerance Robot Controller Reconfiguration

Autoři

PODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z.

Vydáno

30. 8. 2017

Nakladatel

IEEE Computer Society

Místo

Vídeň

ISBN

978-1-5386-2145-5

Kniha

Proceedings of the 2017 20th Euromicro Conference on Digital System Design

Strany od

337

Strany do

344

Strany počet

8

URL

https://www.fit.vut.cz/research/publication/11425/

BibTex

@inproceedings{BUT144431,
  author="Jakub {Podivínský} and Jakub {Lojda} and Ondřej {Čekan} and Richard {Pánek} and Zdeněk {Kotásek}",
  title="Reliability Analysis and Improvement of FPGA-based Robot Controller",
  booktitle="Proceedings of the 2017 20th Euromicro Conference on Digital System Design",
  year="2017",
  pages="337--344",
  publisher="IEEE Computer Society",
  address="Vídeň",
  doi="10.1109/DSD.2017.15",
  isbn="978-1-5386-2145-5",
  url="https://www.fit.vut.cz/research/publication/11425/"
}