Detail publikace

A multi-protocol cache controller

Originální název

A multi-protocol cache controller

Anglický název

A multi-protocol cache controller

Jazyk

en

Originální abstrakt

Bus-based shared memory multiprocessors with per-processor caches use either invalidation or update protocols to maintain cache coherence. This paper suggests mixing protocols for different data objects within a single application, depending on whatever protocol is more efficient for an access pattern to a given object. The model of a two-protocol cache coherence controller has been created in CSP-based Transim language. Each cache line is tagged not only with the state, but also with the protocol type. Two most frequent 4-state, write-back protocols are implemented: MESI (invalidation) and Dragon (update) protocol. The model will be used for experimental evaluation of the proposed controller, which could then be used for processor cores with primary caches in SoC or for secondary caches in multiprocessors with standard microprocessors.

Anglický abstrakt

Bus-based shared memory multiprocessors with per-processor caches use either invalidation or update protocols to maintain cache coherence. This paper suggests mixing protocols for different data objects within a single application, depending on whatever protocol is more efficient for an access pattern to a given object. The model of a two-protocol cache coherence controller has been created in CSP-based Transim language. Each cache line is tagged not only with the state, but also with the protocol type. Two most frequent 4-state, write-back protocols are implemented: MESI (invalidation) and Dragon (update) protocol. The model will be used for experimental evaluation of the proposed controller, which could then be used for processor cores with primary caches in SoC or for secondary caches in multiprocessors with standard microprocessors.

BibTex


@inproceedings{BUT13782,
  author="Vladimír {Kutálek} and Václav {Dvořák}",
  title="A multi-protocol cache controller",
  annote="Bus-based shared memory multiprocessors with per-processor caches use
either invalidation or update protocols to maintain cache coherence.
This paper suggests mixing protocols for different data objects within
a single application, depending on whatever protocol is more efficient
for an access pattern to a given object. The model of a two-protocol
cache coherence controller has been created in CSP-based Transim
language. Each cache line is tagged not only with the state, but also
with the protocol type. Two most frequent 4-state, write-back protocols
are implemented: MESI (invalidation) and Dragon (update) protocol. The
model will be used for experimental evaluation of the proposed
controller, which could then be used for processor cores with primary
caches in SoC or for secondary caches in multiprocessors with standard
microprocessors.",
  address="VŠB - Technical University of Ostrava",
  booktitle="IFAC Workshop on Programmable devices and systems - PDS 2003",
  chapter="13782",
  institution="VŠB - Technical University of Ostrava",
  year="2003",
  month="february",
  pages="220--225",
  publisher="VŠB - Technical University of Ostrava",
  type="conference paper"
}