Detail publikace

A multi-protocol cache controller

KUTÁLEK, V., DVOŘÁK, V.

Originální název

A multi-protocol cache controller

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

Bus-based shared memory multiprocessors with per-processor caches use either invalidation or update protocols to maintain cache coherence. This paper suggests mixing protocols for different data objects within a single application, depending on whatever protocol is more efficient for an access pattern to a given object. The model of a two-protocol cache coherence controller has been created in CSP-based Transim language. Each cache line is tagged not only with the state, but also with the protocol type. Two most frequent 4-state, write-back protocols are implemented: MESI (invalidation) and Dragon (update) protocol. The model will be used for experimental evaluation of the proposed controller, which could then be used for processor cores with primary caches in SoC or for secondary caches in multiprocessors with standard microprocessors.

Klíčová slova

Cache coherence protocols, Bus multiprocessor systems, Tuning characteristics.

Autoři

KUTÁLEK, V., DVOŘÁK, V.

Rok RIV

2003

Vydáno

14. 2. 2003

Nakladatel

VŠB - Technical University of Ostrava

Místo

Ostrava

ISBN

0-08-044130-0

Kniha

IFAC Workshop on Programmable devices and systems - PDS 2003

Strany od

220

Strany do

225

Strany počet

6

BibTex

@inproceedings{BUT13782,
  author="Vladimír {Kutálek} and Václav {Dvořák}",
  title="A multi-protocol cache controller",
  booktitle="IFAC Workshop on Programmable devices and systems - PDS 2003",
  year="2003",
  pages="220--225",
  publisher="VŠB - Technical University of Ostrava",
  address="Ostrava",
  isbn="0-08-044130-0"
}