Detail publikace

HLS-based Fault Tolerance Approach for SRAM-based FPGAs

LOJDA, J. PODIVÍNSKÝ, J. KRČMA, M. KOTÁSEK, Z.

Originální název

HLS-based Fault Tolerance Approach for SRAM-based FPGAs

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper presents an approach to fault-tolerant systems design and synthesis based on High-level Synthesis (HLS). A description and evaluation of the impacts of HLS optimization methods are shown as well. The higher reliability is achieved through modification of input description in the C++ programming language on which the HLS synthesis tools are based on. Our work targets SRAM-based FPGAs, which are prone to Single Event Upsets (SEUs). For the evaluation of impacts of HLS optimization methods we use our evaluation platform, which allows us to test fault tolerance properties of the Design Under Test (DUT). The evaluation platform is based on functional verification combined with fault injection.

Klíčová slova

High Level Synthesis CatapultC Fault Tolerance Robot Controller

Autoři

LOJDA, J.; PODIVÍNSKÝ, J.; KRČMA, M.; KOTÁSEK, Z.

Vydáno

7. 12. 2016

Nakladatel

IEEE Computer Society

Místo

Xi'an

ISBN

978-1-5090-5602-6

Kniha

Proceedings of the 2016 International Conference on Field Programmable Technology

Strany od

301

Strany do

302

Strany počet

2

URL

https://www.fit.vut.cz/research/publication/11275/

BibTex

@inproceedings{BUT131020,
  author="Jakub {Lojda} and Jakub {Podivínský} and Martin {Krčma} and Zdeněk {Kotásek}",
  title="HLS-based Fault Tolerance Approach for SRAM-based FPGAs",
  booktitle="Proceedings of the 2016 International Conference on Field Programmable Technology",
  year="2016",
  pages="301--302",
  publisher="IEEE Computer Society",
  address="Xi'an",
  doi="10.1109/FPT.2016.7929561",
  isbn="978-1-5090-5602-6",
  url="https://www.fit.vut.cz/research/publication/11275/"
}