Detail publikace

Instruction mapping process on the VLIW architectures

Originální název

Instruction mapping process on the VLIW architectures

Anglický název

Instruction mapping process on the VLIW architectures

Jazyk

en

Originální abstrakt

This paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.

Anglický abstrakt

This paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.

BibTex


@inproceedings{BUT124268,
  author="Roman {Mego}",
  title="Instruction mapping process on the VLIW architectures",
  annote="This paper deals with the process of instruction mapping on the digital signal processors.
This process is used by the newly developed tool, which is designed for generating low-level assembly
code for very long instruction word processors. The tool is suitable for creating cores of the
signal processing algorithms.",
  address="Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií",
  booktitle="Proceedings of the 22nd conference Student EEICT",
  chapter="124268",
  howpublished="electronic, physical medium",
  institution="Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií",
  year="2016",
  month="april",
  pages="385--389",
  publisher="Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií",
  type="conference paper"
}