Detail publikace

CRC based hashing in FPGA using DSP blocks

ZÁVODNÍK, T. KEKELY, L. PUŠ, V.

Originální název

CRC based hashing in FPGA using DSP blocks

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

We propose a novel approach to the computation of the CRC functions, commonly used for bit error checking purposes when handling binary data. This approach is designed for general hashing purposes in FPGA, for which the CRCs are usable as well. The method is suitable for applications which use parallel inputs of fixed size and require high throughput, such as hash tables. We employ the DSP blocks present in modern FPGAs to perform all the necessary XOR operations, so that our solution does not consume any LUTs. We propose a Monte Carlo based heuristic to reduce the number of the DSP blocks required by the computation. Our experimental results show that one DSP block capable of 48 XOR operations can replace around eleven 6-input LUTs.

Klíčová slova

FPGA, CRC, DSP, Hash

Autoři

ZÁVODNÍK, T.; KEKELY, L.; PUŠ, V.

Rok RIV

2014

Vydáno

23. 4. 2014

Nakladatel

IEEE Computer Society

Místo

Warszawa

ISBN

978-1-4799-4558-0

Kniha

17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

Strany od

179

Strany do

182

Strany počet

4

URL

https://www.fit.vut.cz/research/publication/10614/

BibTex

@inproceedings{BUT111578,
  author="Tomáš {Závodník} and Lukáš {Kekely} and Viktor {Puš}",
  title="CRC based hashing in FPGA using DSP blocks",
  booktitle="17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2014",
  pages="179--182",
  publisher="IEEE Computer Society",
  address="Warszawa",
  doi="10.1109/DDECS.2014.6868786",
  isbn="978-1-4799-4558-0",
  url="https://www.fit.vut.cz/research/publication/10614/"
}