Detail publikace

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

MIČULKA, L. STRAKA, M. KOTÁSEK, Z.

Originální název

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

Anglický název

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

Jazyk

en

Originální abstrakt

The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.

Anglický abstrakt

The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.

Dokumenty

BibTex 


@inproceedings{BUT103518,
  author="Lukáš {Mičulka} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area",
  annote="The paper presents a methodology of fault tolerant system design into an FPGA
with the ability of the transient fault and the permanent fault mitigation. The
transient fault mitigation is done by the partial dynamic reconfiguration. The
mitigation of a certain number of permanent faults is based on using a specific
fault tolerant architecture occupiing less resources than the previosly used one
and excluding the faulty part of the FPGA. This inovative technique is based on
the precompiled configurations stored in an external memory. To reduce the
required space for a partial bitstream the relocation technique is used.",
  address="IEEE Computer Society",
  booktitle="16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools",
  chapter="103518",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2013",
  month="march",
  pages="227--234",
  publisher="IEEE Computer Society",
  type="conference paper"
}