Detail publikace

Towards Evolvable Systems Based on the Xilinx Zynq Platform

Originální název

Towards Evolvable Systems Based on the Xilinx Zynq Platform

Anglický název

Towards Evolvable Systems Based on the Xilinx Zynq Platform

Jazyk

en

Originální abstrakt

Field programmable gate arrays (FPGAs) are considered as a good platform for digital evolvable hardware systems. Researchers introduced virtual reconfigurable circuits as the response to the insufficient support of partial reconfiguration in early FPGAs. Later, the features of FPGAs allowed the designers to develop evolvable systems fully exploiting native reconfiguration infrastructures. Xilinx recently introduced a new platform called Zynq-7000 all programmable (AP) system-on-chip (SoC) which has the potential to become the next revolutionary step in evolvable hardware design. The paper analyzes Zynq-7000 AP SoC from the perspective of an evolvable hardware designer. Several scenarios are described of how to implement evolvable systems on a developmental board equipped with this programmable SoC. These scenarios are evaluated in terms of area overhead, execution time, reconfiguration time and throughput. The resulting observations should be useful for those who are going to develop real-world evolvable systems on the Zynq-7000 AP SoC platform.

Anglický abstrakt

Field programmable gate arrays (FPGAs) are considered as a good platform for digital evolvable hardware systems. Researchers introduced virtual reconfigurable circuits as the response to the insufficient support of partial reconfiguration in early FPGAs. Later, the features of FPGAs allowed the designers to develop evolvable systems fully exploiting native reconfiguration infrastructures. Xilinx recently introduced a new platform called Zynq-7000 all programmable (AP) system-on-chip (SoC) which has the potential to become the next revolutionary step in evolvable hardware design. The paper analyzes Zynq-7000 AP SoC from the perspective of an evolvable hardware designer. Several scenarios are described of how to implement evolvable systems on a developmental board equipped with this programmable SoC. These scenarios are evaluated in terms of area overhead, execution time, reconfiguration time and throughput. The resulting observations should be useful for those who are going to develop real-world evolvable systems on the Zynq-7000 AP SoC platform.

BibTex


@inproceedings{BUT103436,
  author="Roland {Dobai} and Lukáš {Sekanina}",
  title="Towards Evolvable Systems Based on the Xilinx Zynq Platform",
  annote="Field programmable gate arrays (FPGAs) are considered as a good platform for
digital evolvable hardware systems. Researchers introduced virtual reconfigurable
circuits as the response to the insufficient support of partial reconfiguration
in early FPGAs. Later, the features of FPGAs allowed the designers to develop
evolvable systems fully exploiting native reconfiguration infrastructures. Xilinx
recently introduced a new platform called Zynq-7000 all programmable (AP)
system-on-chip (SoC) which has the potential to become the next revolutionary
step in evolvable hardware design. The paper analyzes Zynq-7000 AP SoC from the
perspective of an evolvable hardware designer. Several scenarios are described of
how to implement evolvable systems on a developmental board equipped with this
programmable SoC. These scenarios are evaluated in terms of area overhead,
execution time, reconfiguration time and throughput. The resulting observations
should be useful for those who are going to develop real-world evolvable systems
on the Zynq-7000 AP SoC platform.",
  address="IEEE Computational Intelligence Society",
  booktitle="2013 IEEE International Conference on Evolvable Systems (ICES)",
  chapter="103436",
  doi="10.1109/ICES.2013.6613287",
  edition="Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)",
  howpublished="electronic, physical medium",
  institution="IEEE Computational Intelligence Society",
  year="2013",
  month="april",
  pages="89--95",
  publisher="IEEE Computational Intelligence Society",
  type="conference paper"
}