Detail publikace

On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

Originální název

On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

Anglický název

On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

Jazyk

en

Originální abstrakt

The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to preprocess all interrupts before they arrive to the system. The hardware is ready to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper.

Anglický abstrakt

The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to preprocess all interrupts before they arrive to the system. The hardware is ready to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper.

BibTex


@inproceedings{BUT103418,
  author="Josef {Strnadel}",
  title="On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems",
  annote="The paper details design of a hardware unit for preventing real-time systems from
overloads caused by excessive interrupt rates. Novelty of the hardware can be
seen in the fact it is able to adapt interrupt service rate to the RT system load
and to the actual priority assignment policy. The load is monitored on basis of
special low-overhead signals produced by the system for this purpose. The
hardware is designed to preprocess all interrupts before they arrive to the
system. The hardware is ready to buffer each interrupt-related communication
until the system is underloaded or running an activity having a lower priority
comparing to the interrupt. Design of the hardware was described in VHDL and
synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks,
overheads and limits related to the realization are presented in this paper.",
  address="IEEE Computer Society",
  booktitle="Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  chapter="103418",
  doi="10.1109/DDECS.2013.6549783",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2013",
  month="april",
  pages="24--29",
  publisher="IEEE Computer Society",
  type="conference paper"
}