Detail publikace

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Originální název

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Anglický název

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Jazyk

en

Originální abstrakt

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only +-0.4 V and the power consumption is 23.5 uW. PSpice simulation results using the 0.18 um CMOS technology from TSMC are included to verify the design functionality and correspondence with theory.

Anglický abstrakt

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only +-0.4 V and the power consumption is 23.5 uW. PSpice simulation results using the 0.18 um CMOS technology from TSMC are included to verify the design functionality and correspondence with theory.

BibTex


@article{BUT98979,
  author="Fabian {Khateb} and Salma {Bay Abo Dabbous} and Spyridon {Vlassis}",
  title="A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design",
  annote="Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only +-0.4 V and the power consumption is 23.5 uW. PSpice simulation results using the 0.18 um CMOS technology from TSMC are included to verify the design functionality and correspondence with theory.",
  chapter="98979",
  number="2, IF: 0.687",
  volume="2013 (22)",
  year="2013",
  month="june",
  pages="415--427",
  type="journal article in Web of Science"
}