Detail publikace

Speeding-up OAS and AAS Communication in Networking System on Chips

JAROŠ, J., DVOŘÁK, V.

Originální název

Speeding-up OAS and AAS Communication in Networking System on Chips

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

As chip multiprocessors are quickly penetrating new application areas in network and media processing, their interconnection architectures become a subject of optimization. Group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology using WH (Wormhole) switching.

Klíčová slova

BOA algorithm, communication patterns, multiprocessor topology, hypercube, AMP

Autoři

JAROŠ, J., DVOŘÁK, V.

Rok RIV

2005

Vydáno

21. 4. 2005

Nakladatel

University of West Hungary

Místo

Sopron

ISBN

9639364487

Kniha

Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems

Strany od

206

Strany do

209

Strany počet

4

BibTex

@inproceedings{BUT21469,
  author="Jiří {Jaroš} and Václav {Dvořák}",
  title="Speeding-up OAS and AAS Communication in Networking System on Chips",
  booktitle="Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems",
  year="2005",
  pages="4",
  publisher="University of West Hungary",
  address="Sopron",
  isbn="9639364487"
}