Detail publikace

BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE

Originální název

BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE

Anglický název

BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE

Jazyk

en

Originální abstrakt

This article describes the implementation of a RocketIO bit-error rate tester (BERT) on the DSP custom board FD64x. The BER test is aimed at the serial link between two transceivers placed in the Virtex-II Pro FPGA. The tester module generating PRBS pattern, verifying received data and counting bit errors.

Anglický abstrakt

This article describes the implementation of a RocketIO bit-error rate tester (BERT) on the DSP custom board FD64x. The BER test is aimed at the serial link between two transceivers placed in the Virtex-II Pro FPGA. The tester module generating PRBS pattern, verifying received data and counting bit errors.

BibTex


@inproceedings{BUT19450,
  author="Zdeněk {Bradáč} and Soběslav {Valach}",
  title="BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE",
  annote="This article describes the implementation of a RocketIO bit-error rate tester
(BERT) on the DSP custom board FD64x. The BER test is aimed at the serial link
between two transceivers placed in the Virtex-II Pro FPGA. The tester module generating
PRBS pattern, verifying received data and counting bit errors.",
  address="VUT Brno",
  booktitle="Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003",
  chapter="19450",
  institution="VUT Brno",
  year="2006",
  month="february",
  pages="433",
  publisher="VUT Brno",
  type="conference paper"
}