Detail publikace

Analysis of OTA-Based Gyrator Implementing Fractional-Order Inductor

KUBÁNEK, D. KOTON, J. DVOŘÁK, J. HERENCSÁR, N. ŠOTNER, R.

Originální název

Analysis of OTA-Based Gyrator Implementing Fractional-Order Inductor

Anglický název

Analysis of OTA-Based Gyrator Implementing Fractional-Order Inductor

Jazyk

en

Originální abstrakt

An analysis of fractional-order inductor implemented by operational transconductance amplifier (OTA)-based gyrator loaded with an ideal fractional-order capacitor is presented. The impact of OTA parasitic properties on the gyrator functionality is demonstrated. The affected input admittance characteristics are included along with the relations for important values and cut-off frequencies in these characteristics. Design recommendations are provided to reduce the effect of the parasitics. The theoretical assumptions are validated by computer simulation with high-frequency model of a CMOS OTA. The constraints regarding dynamic range are also discussed.

Anglický abstrakt

An analysis of fractional-order inductor implemented by operational transconductance amplifier (OTA)-based gyrator loaded with an ideal fractional-order capacitor is presented. The impact of OTA parasitic properties on the gyrator functionality is demonstrated. The affected input admittance characteristics are included along with the relations for important values and cut-off frequencies in these characteristics. Design recommendations are provided to reduce the effect of the parasitics. The theoretical assumptions are validated by computer simulation with high-frequency model of a CMOS OTA. The constraints regarding dynamic range are also discussed.

Dokumenty

BibTex


@inproceedings{BUT165352,
  author="David {Kubánek} and Jaroslav {Koton} and Jan {Dvořák} and Norbert {Herencsár} and Roman {Šotner}",
  title="Analysis of OTA-Based Gyrator Implementing Fractional-Order Inductor",
  annote="An analysis of fractional-order inductor implemented by operational transconductance amplifier (OTA)-based gyrator loaded with an ideal fractional-order capacitor is presented. The impact of OTA parasitic properties on the gyrator functionality is demonstrated. The affected input admittance characteristics are included along with the relations for important values and cut-off frequencies in these characteristics. Design recommendations are provided to reduce the effect of the parasitics. The theoretical assumptions are validated by computer simulation with high-frequency model of a CMOS OTA. The constraints regarding dynamic range are also discussed.",
  address="IEEE",
  booktitle="Proceedings of the 2020 43rd International Conference on Telecommunications and Signal Processing (TSP), Milan, Italy",
  chapter="165352",
  doi="10.1109/TSP49548.2020.9163406",
  howpublished="online",
  institution="IEEE",
  year="2020",
  month="july",
  pages="583--588",
  publisher="IEEE",
  type="conference paper"
}