Detail publikace

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study

PODIVÍNSKÝ, J. ČEKAN, O. KRČMA, M. BURGET, R. HRUŠKA, T. KOTÁSEK, Z.

Originální název

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study

Anglický název

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study

Jazyk

en

Originální abstrakt

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a processor is used in multiple designs. The goal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Anglický abstrakt

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a processor is used in multiple designs. The goal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Dokumenty

BibTex


@inproceedings{BUT159969,
  author="Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Radek {Burget} and Tomáš {Hruška} and Zdeněk {Kotásek}",
  title="Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study",
  annote="Almost every today's electronic devices are equipped with a processor. Different
applications require and depend on different properties of a processor. For
example, the fast growing field of Internet of Things depends on a long operation
time of the devices when powered with batteries. Using a general purpose
processors has proved ineffective which led to growing usage of
Application-Specific Instruction-Set processors (ASIPs) which can be optimized to
specific applications using different modifications of their properties (such as
the number of registers, cache sizes, instruction set modifications, etc.).
A suitable processor configuration can be hand-picked by a designer or by an
automatic tool. Such a tool was developed in our previous research. It is able to
find a set of Pareto-optimal processor configurations for a specific application
which can be a significant help in a device design. The cost of the design
process can be cut significantly when a processor is used in multiple designs.
The goal of this paper is to introduce a tool able to find a suitable processor
configuration for multiple application by constructing a compromise
Pareto-optimal frontier of a processor configurations. The paper describes this
problem on a theoretical level as well as it introduces a practical
implementation and experimental evaluation of constructing a compromise Pareto
frontier of a processor configurations for a set of applications. The experiments
are based on a parameterizable RISC-V processor.",
  address="Institute of Electrical and Electronics Engineers",
  booktitle="Proceedings of the 2019 22nd Euromicro Conference on Digital System Design",
  chapter="159969",
  doi="10.1109/DSD.2019.00091",
  edition="NEUVEDEN",
  howpublished="electronic, physical medium",
  institution="Institute of Electrical and Electronics Engineers",
  year="2019",
  month="august",
  pages="597--600",
  publisher="Institute of Electrical and Electronics Engineers",
  type="conference paper"
}