Detail publikace

Sub-Volt Bulk-Driven Transconductance Amplifier and Filter Application

Originální název

Sub-Volt Bulk-Driven Transconductance Amplifier and Filter Application

Anglický název

Sub-Volt Bulk-Driven Transconductance Amplifier and Filter Application

Jazyk

en

Originální abstrakt

This paper describes a low-voltage and low-power transconductance amplifier and its application to third-order elliptic low-pass filter. The bulk-driven MOS transistor technique is used to provide low supply voltage operation and rail-to-rail input voltage common mode. The performance of the proposed filter is expressed through PSPICE simulators using TSMC 0.18 mu m n-well CMOS process. Simulation results show that the filter using proposed circuit consumes 36 mu W for power supply of a 0.5 V and has total harmonic distortion 1 % for input signal of 480 mV(P-P).

Anglický abstrakt

This paper describes a low-voltage and low-power transconductance amplifier and its application to third-order elliptic low-pass filter. The bulk-driven MOS transistor technique is used to provide low supply voltage operation and rail-to-rail input voltage common mode. The performance of the proposed filter is expressed through PSPICE simulators using TSMC 0.18 mu m n-well CMOS process. Simulation results show that the filter using proposed circuit consumes 36 mu W for power supply of a 0.5 V and has total harmonic distortion 1 % for input signal of 480 mV(P-P).

BibTex


@inproceedings{BUT155908,
  author="Montree {Kumngern} and Usa {Torteanchai} and Sathian {Yutthanaboon} and Fabian {Khateb}",
  title="Sub-Volt Bulk-Driven Transconductance Amplifier and Filter Application",
  annote="This paper describes a low-voltage and low-power transconductance amplifier and its application to third-order elliptic low-pass filter. The bulk-driven MOS transistor technique is used to provide low supply voltage operation and rail-to-rail input voltage common mode. The performance of the proposed filter is expressed through PSPICE simulators using TSMC 0.18 mu m n-well CMOS process. Simulation results show that the filter using proposed circuit consumes 36 mu W for power supply of a 0.5 V and has total harmonic distortion 1 % for input signal of 480 mV(P-P).",
  address="IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA",
  booktitle="14th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)",
  chapter="155908",
  doi="10.1109/APCCAS.2018.8605640",
  howpublished="print",
  institution="IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA",
  year="2019",
  month="february",
  pages="1--4",
  publisher="IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA",
  type="conference paper"
}