Detail publikace

FPGA Implementation of Multiplierless Low-Pass FIR Differentiator

SOVA, V. BRABLC, M. GREPL, R.

Originální název

FPGA Implementation of Multiplierless Low-Pass FIR Differentiator

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

In this paper we present, that if we appropriately choose the parameters of the maximally flat FIR differentiator, the coefficients of the filter will have a common divisor which is reciprocal to a power of two. That means that the entire filter can be implemented in a very cost-effective way using only shift and add operations, which is beneficial mainly when the filter is implemented on the FPGA. Proposed differentiator was implemented on an FPGA and tested in real time. At the end of the article we compare the FPGA resource utilization for the proposed maximally-flat FIR differentiator and a differentiator designed using a common approach.

Klíčová slova

differentiator, FPGA, multiplierless, FIR

Autoři

SOVA, V.; BRABLC, M.; GREPL, R.

Vydáno

23. 1. 2019

ISBN

978-80-214-5542-9

Kniha

PROCEEDINGS OF THE 2018 18TH INTERNATIONAL CONFERENCE ON MECHATRONICS - MECHATRONIKA (ME)

Strany od

382

Strany do

386

Strany počet

5

BibTex

@inproceedings{BUT152524,
  author="Václav {Sova} and Martin {Brablc} and Robert {Grepl}",
  title="FPGA Implementation of Multiplierless Low-Pass FIR Differentiator",
  booktitle="PROCEEDINGS OF THE 2018 18TH INTERNATIONAL CONFERENCE ON MECHATRONICS - MECHATRONIKA (ME)",
  year="2019",
  pages="382--386",
  isbn="978-80-214-5542-9"
}