Detail publikace

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

KULEJ, T. KHATEB, F. FERREIRA, L.

Originální název

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

Anglický název

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

Jazyk

en

Originální abstrakt

A new solution for an ultra-low-voltage bulk-driven asynchronous delta sigma modulator (ADSM) is described in the paper. While implemented in a standard 0.18 um CMOS process from TSMC and supplied with VDD = 0.3 V, the circuit offers a 53.3 dB signal to noise and distortion ratio (SNDR), which corresponds to 8.56-bit resolution. Besides, the total power consumption is 37 nW, the signal bandwidth is 62 Hz and the resulting power efficiency is 0.79 pJ/conversion. The above features have been achieved employing a highly linear operational transconductance amplifier (OTA) and a hysteretic comparator based on non-tailed differential pair.

Anglický abstrakt

A new solution for an ultra-low-voltage bulk-driven asynchronous delta sigma modulator (ADSM) is described in the paper. While implemented in a standard 0.18 um CMOS process from TSMC and supplied with VDD = 0.3 V, the circuit offers a 53.3 dB signal to noise and distortion ratio (SNDR), which corresponds to 8.56-bit resolution. Besides, the total power consumption is 37 nW, the signal bandwidth is 62 Hz and the resulting power efficiency is 0.79 pJ/conversion. The above features have been achieved employing a highly linear operational transconductance amplifier (OTA) and a hysteretic comparator based on non-tailed differential pair.

Dokumenty

BibTex 


@article{BUT149480,
  author="Tomasz {Kulej} and Fabian {Khateb} and Luis H. C. {Ferreira}",
  title="A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS",
  annote="A new solution for an ultra-low-voltage bulk-driven asynchronous delta sigma modulator (ADSM) is described in the paper. While implemented in a standard 0.18 um CMOS process from TSMC and supplied with VDD = 0.3 V, the circuit offers a 53.3 dB signal to noise and distortion ratio (SNDR), which corresponds to 8.56-bit resolution. Besides, the total power consumption is 37 nW, the signal bandwidth is 62 Hz and the resulting power efficiency is 0.79 pJ/conversion. The above features have been achieved employing a highly linear operational transconductance amplifier (OTA) and a hysteretic comparator based on non-tailed differential pair.",
  address="IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",
  chapter="149480",
  doi="10.1109/TVLSI.2018.2878625",
  howpublished="print",
  institution="IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",
  number="2, IF: 1.946",
  volume="27",
  year="2019",
  month="january",
  pages="316--325",
  publisher="IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",
  type="journal article in Web of Science"
}