Detail publikace

0.3-V Bulk-driven Programmable Gain Amplifier in 0.18 um CMOS

Originální název

0.3-V Bulk-driven Programmable Gain Amplifier in 0.18 um CMOS

Anglický název

0.3-V Bulk-driven Programmable Gain Amplifier in 0.18 um CMOS

Jazyk

en

Originální abstrakt

A new solution for an ultra low voltage bulk-driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n-well 0.18 um CMOS process the circuit operates from 0.3 V supply and its voltage gain can be regulated from 0 to 18 dB with 6 dB steps. At minimum gain the PGA offers nearly rail-to-rail input/output swing and the input referred thermal noise of 2.37 uV/Hz1/2, which results in a 63 dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5 pF load capacitance and the third order input intercept point (IIP3) is 1.62 V. The circuit performance was simulated with LTspice.

Anglický abstrakt

A new solution for an ultra low voltage bulk-driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n-well 0.18 um CMOS process the circuit operates from 0.3 V supply and its voltage gain can be regulated from 0 to 18 dB with 6 dB steps. At minimum gain the PGA offers nearly rail-to-rail input/output swing and the input referred thermal noise of 2.37 uV/Hz1/2, which results in a 63 dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5 pF load capacitance and the third order input intercept point (IIP3) is 1.62 V. The circuit performance was simulated with LTspice.

BibTex


@article{BUT127361,
  author="Tomasz {Kulej} and Fabian {Khateb}",
  title="0.3-V Bulk-driven Programmable Gain Amplifier  in 0.18 um CMOS",
  annote="A new solution for an ultra low voltage bulk-driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n-well 0.18 um CMOS process the circuit operates from 0.3 V supply and its voltage gain can be regulated from 0 to 18 dB with 6 dB steps. At minimum gain the PGA offers nearly rail-to-rail input/output swing and the input referred thermal noise of 2.37 uV/Hz1/2, which results in a 63 dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5 pF load capacitance and the third order input intercept point (IIP3) is 1.62 V. The circuit performance was simulated with LTspice.",
  address="WILEY-BLACKWELL",
  chapter="127361",
  doi="10.1002/cta.2269",
  howpublished="print",
  institution="WILEY-BLACKWELL",
  number="8, IF: 1.571",
  volume="2017 (45)",
  year="2017",
  month="august",
  pages="1077--1094",
  publisher="WILEY-BLACKWELL",
  type="journal article in Web of Science"
}