Detail publikace

Low-voltage low-power bulk-driven analog median filter

Originální název

Low-voltage low-power bulk-driven analog median filter

Anglický název

Low-voltage low-power bulk-driven analog median filter

Jazyk

en

Originální abstrakt

This paper presents low-voltage (LV) low-power (LP) voltage-mode analog median filter based on winner-take-all (WTA) and loser-take-all (LTA) circuits. The LTA and WTA CMOS structures are performed utilizing bulk-driven (BD) MOS transistor (MOST) technique, enabling circuits to operate under low supply voltage of only ±0.25 V and consume extremely low-power in micro range. In addition to the simple topology of the proposed circuits, they provide high accuracy. Moreover, the common mode voltage range is near rail-to-rail. Eventually, to verify the functionality of the proposed circuits, the simulation results are carried out in Cadence environment using triple-well 0.18 µm CMOS process.

Anglický abstrakt

This paper presents low-voltage (LV) low-power (LP) voltage-mode analog median filter based on winner-take-all (WTA) and loser-take-all (LTA) circuits. The LTA and WTA CMOS structures are performed utilizing bulk-driven (BD) MOS transistor (MOST) technique, enabling circuits to operate under low supply voltage of only ±0.25 V and consume extremely low-power in micro range. In addition to the simple topology of the proposed circuits, they provide high accuracy. Moreover, the common mode voltage range is near rail-to-rail. Eventually, to verify the functionality of the proposed circuits, the simulation results are carried out in Cadence environment using triple-well 0.18 µm CMOS process.

BibTex


@article{BUT122250,
  author="Fabian {Khateb} and Montree {Kumngern} and Salma {Bay Abo Dabbous} and Tomasz {Kulej}",
  title="Low-voltage low-power bulk-driven analog median filter",
  annote="This paper presents low-voltage (LV) low-power (LP) voltage-mode analog median filter based on winner-take-all (WTA) and loser-take-all (LTA) circuits. The LTA and WTA CMOS structures are performed utilizing bulk-driven (BD) MOS transistor (MOST) technique, enabling circuits to operate under low supply voltage of only ±0.25 V and consume extremely low-power in micro range. In addition to the simple topology of the proposed circuits, they provide high accuracy. Moreover, the common mode voltage range is near rail-to-rail. Eventually, to verify the functionality of the proposed circuits, the simulation results are carried out in Cadence environment using triple-well 0.18 µm CMOS process.",
  address="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  chapter="122250",
  doi="10.1016/j.aeue.2016.02.007",
  howpublished="print",
  institution="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  number="5, IF: 0.786",
  volume="2016 (70)",
  year="2016",
  month="february",
  pages="698--706",
  publisher="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  type="journal article in Web of Science"
}