Detail publikace

Memristor Model For Massively-Parallel Computations

Originální název

Memristor Model For Massively-Parallel Computations

Anglický název

Memristor Model For Massively-Parallel Computations

Jazyk

en

Originální abstrakt

The model of memristor described in the paper is designed for building models of large networks for analog computations. A circuit containing thousands of memristors for finding the shortest path in a complicated maze is a typical example. The model is designed to meet the following criteria: 1. It is a model of HP memristor with linear dopant drift while respecting the physical bounds of the internal state variable. 2. Reliable operation in the SPICE environment also when simulating extremely large networks. 3. Minimization of the simulation time while computing bias points and during transient analyses. A benchmark circuit for testing the applications of various complexities is presented. The results confirm a perfect operation of the model also in applications containing thousands of memristors.

Anglický abstrakt

The model of memristor described in the paper is designed for building models of large networks for analog computations. A circuit containing thousands of memristors for finding the shortest path in a complicated maze is a typical example. The model is designed to meet the following criteria: 1. It is a model of HP memristor with linear dopant drift while respecting the physical bounds of the internal state variable. 2. Reliable operation in the SPICE environment also when simulating extremely large networks. 3. Minimization of the simulation time while computing bias points and during transient analyses. A benchmark circuit for testing the applications of various complexities is presented. The results confirm a perfect operation of the model also in applications containing thousands of memristors.

BibTex


@inproceedings{BUT119677,
  author="Dalibor {Biolek} and Viera {Biolková} and Zdeněk {Kolka}",
  title="Memristor Model For Massively-Parallel Computations",
  annote="The model of memristor described in the paper is designed for building models of large networks for analog computations. A circuit containing thousands of memristors for finding the shortest path in a complicated maze is a typical example. The model is designed to meet the following criteria: 1. It is a model of HP memristor with linear dopant drift while respecting the physical bounds of the internal state variable. 2. Reliable operation in the SPICE environment also when simulating extremely large networks. 3. Minimization of the simulation time while computing bias points and during transient analyses. A benchmark circuit for testing the applications of various complexities is presented. The results confirm a perfect operation of the model also in applications containing thousands of memristors.",
  address="IEEE",
  booktitle="2015 International Conference on Computing, Communication and Security (ICCCS)",
  chapter="119677",
  howpublished="electronic, physical medium",
  institution="IEEE",
  year="2015",
  month="december",
  pages="410--414",
  publisher="IEEE",
  type="conference paper"
}